Abstract: A signal processing method and apparatus, where the apparatus includes an input interface configured to receive an input signal matrix and a weight matrix, a processor configured to interleave the input signal matrix to obtain an interleaved signal matrix, partition the interleaved signal matrix, interleave the weight matrix to obtain an interleaved weight matrix, process the interleaved weight matrix to obtain a plurality of sparsified partitioned weight matrices, perform matrix multiplication on the sparsified partitioned weight matrices and a plurality of partitioned signal matrices to obtain a plurality of matrix multiplication results, and an output interface configured to output a signal processing result.

Abstract: A Heisenberg scaler reduces noise in quantum metrology and includes: a stimulus source that provides physical stimuli; a physical system including quantum sensors that receive a first and second physical stimuli; produces a measured action parameter; receives an perturbation pulse; and produces modal amplitude; an estimation machine that: receives the measured action parameter and produces a zeroth-order value from the measured action parameter; a gradient analyzer that: receives the measured action parameter and produces the measured action parameter and a gradient; the sensor interrogation unit that: receives the modal amplitude; receives the gradient and the measured action parameter; produces the perturbation pulse; and produces a first-order value from the modal amplitude, the gradient, and the measured action parameter; a Heisenberg determination machine that: receives the zeroth-order value; receives the first-order value; and produces a physical scalar from the zeroth-order value and the first-order v

Abstract: Disclosed is a neural network accelerator including a first bit operator generating a first multiplication result by performing multiplication on first feature bits of input feature data and first weight bits of weight data, a second bit operator generating a second multiplication result by performing multiplication on second feature bits of the input feature data and second weight bits of the weight data, an adder generating an addition result by performing addition based on the first multiplication result and the second multiplication result, a shifter shifting a number of digits of the addition result depending on a shift value to generate a shifted addition result, and an accumulator generating output feature data based on the shifted addition result.

Abstract: The present disclosure relates to a method and an apparatus for approximating non-linear function. In some embodiments, an exemplary processing unit includes: one or more registers for storing a lookup table (LUT) and one or more operation elements communicatively coupled with the one or more registers. The LUT includes a control state and a plurality of data entries. The one or more operation elements are configured to: receive an input operand; select one or more bits from the input operand; select a data entry from the plurality of data entries using the one or more bits; and determine an approximation value of a non-linear activation function for the input operand using the data entry.

Abstract: An apparatus for convolution operation is provided.

Abstract: Quantum computing systems and methods are provided. In one example, a quantum computing system includes a quantum system having one or more quantum system qubits and one or more ancilla qubits. The quantum computing system includes one or more quantum gates implemented by the quantum computing system. The quantum gate(s) are operable to configure the one or more ancilla qubits into a known state. The quantum computing system includes a quantum measurement circuit operable to perform a plurality of measurements on the one or more quantum system qubits using the one or more ancilla qubits. The quantum computing system includes one or more processors operable to determine a reduced density matrix for a subset of the quantum system based on a set of the plurality of measurements that include a number of repeated measurements performed using the quantum measurement circuit.

Abstract: At least one machine-accessible storage medium that provides instructions that, when executed by a machine, will cause the machine to perform operations. The operations comprise configuring a simulated environment to be representative of a physical device based, at least in part, on an initial description of the physical device that described structural parameters of the physical device. The operations further comprise performing a physics simulation with an artificial intelligence (“AI”) accelerator. The AI accelerator includes a matrix multiply unit for computing convolution operations via a plurality of multiply-accumulate units. The operations further comprise computing a field response in response of the physical device in response to an excitation source within the simulated environment when performing the physics simulation. The field response is computed, at least in part, with the convolution operations to perform spatial differencing.

Abstract: The present disclosure relates to a neuron for an artificial neural network. The neuron includes: a first dot product engine operative to: receive a first set of weights; receive a set of inputs; and calculate the dot product of the set of inputs and the first set of weights to generate a first dot product engine output. The neuron further includes a second dot product engine operative to: receive a second set of weights; receive an input based on the first dot product engine output; and generate a second dot product engine output based on the product of the first dot product engine output and a weight of the second set of weights. The neuron further includes an activation function module arranged to generate a neuron output based on the second dot product engine output. The first dot product engine and the second dot product engine are structurally or functionally different.

Abstract: A method, computer software product and system for solving cyclic scheduling problems. Specifically, the present disclosure significantly improves the method in a previous patent (H. K. Alfares, 2011, “Cyclic Combinatorial Method and System”, U.S. Pat. No. 8,046,316), by eliminating a time-consuming combinatorial procedure. A procedure is described which significantly decreases the number of iterations, and hence computational time and cost. The processes of the present disclosure have many applications in cyclic workforce scheduling, cyclic transportation system scheduling, cyclic scheduling of data packet transmitting as applied to networks having a plurality of nodes and cyclic production scheduling.

Abstract: The present disclosure relates to an apparatus for decoding an encoded Unified Audio and Speech stream. The apparatus comprises a core decoder for decoding the encoded Unified Audio and Speech stream. The core decoder includes a fast Fourier transform, FFT, module implementation based on a Cooley-Tuckey algorithm. The FFT module is configured to determine a discrete Fourier transform, DFT. Determining the DFT involves recursively breaking down the DFT into small FFTs based on the Cooley-Tucker algorithm and using radix-4 if a number of points of the FFT is a power of 4 and using mixed radix if the number is not a power of 4. Performing the small FFTs involves applying twiddle factors. Applying the twiddle factors involves referring to pre-computed values for the twiddle factors.

Abstract: Some embodiments provide a method for a neural network inference circuit that executes a neural network including computation nodes at multiple layers. Each of a set of the nodes includes a dot product of input values and weight values. The method reads multiple input values for a particular layer from a memory location of the circuit. A first set of the input values are used for a first dot product for a first node of the layer. The method stores the input values in a cache. The method computes the first dot product for the first node using the first set of input values. Without requiring a read of any input values from any additional memory locations, the method computes a second dot product for a second node of the particular layer using a subset of the first set of input values and a second set of the input values.

Abstract: A novel and useful neural network (NN) processing core adapted to implement artificial neural networks (ANNs) and incorporating processing circuits having compute and local memory elements. The NN processor is constructed from self-contained computational units organized in a hierarchical architecture. The homogeneity enables simpler management and control of similar computational units, aggregated in multiple levels of hierarchy. Computational units are designed with minimal overhead as possible, where additional features and capabilities are aggregated at higher levels in the hierarchy. On-chip memory provides storage for content inherently required for basic operation at a particular hierarchy and is coupled with the computational resources in an optimal ratio. Lean control provides just enough signaling to manage only the operations required at a particular hierarchical level.

Abstract: The present disclosure advantageously provides a modulo operation unit that includes a first input configured to receive operand data, a second input configured to receive modulus data, an initial modulo stage, a sequence of intermediate modulo stages, and a final modulo stage.

Abstract: Techniques for performing in-memory matrix multiplication, taking into account temperature variations in the memory, are disclosed. In one example, the matrix multiplication memory uses ohmic multiplication and current summing to perform the dot products involved in matrix multiplication. One downside to this analog form of multiplication is that temperature affects the accuracy of the results. Thus techniques are provided herein to compensate for the effects of temperature increases on the accuracy of in-memory matrix multiplications. According to the techniques, portions of input matrices are classified as effective or ineffective. Effective portions are mapped to low temperature regions of the in-memory matrix multiplier and ineffective portions are mapped to high temperature regions of the in-memory matrix multiplier. The matrix multiplication is then performed.

Abstract: Full adder, a chip and a computing device are disclosed. A full adder includes: a plurality of primary logic cells and at least one secondary logic cell, wherein an output terminal of each primary logic cell is at least connected to an input terminal of a first secondary logic cell in the at least one secondary logic cell. The plurality of primary logic cells includes: a first primary logic cell, a second primary logic cell and a third primary logic cell respectively configured to generate a first intermediate signal, a second intermediate signal and a carry-related signal based on a first input signal, a second input signal and a carry input signal input to the full adder. Furthermore, the first secondary logic cell is configured to generate a sum output signal of the full adder based on the first intermediate signal, the second intermediate signal and the carry-related signal.

Abstract: Methods, systems, and apparatus, including instructions encoded on storage media, for performing reduction of gradient vectors and similarly structured data that are generated in parallel, for example, on nodes organized in a mesh or torus topology defined by connections in at least two dimension between the nodes. The methods provide parallel computation and communication between nodes in the topology.

Abstract: Methods, systems, and apparatus for a matrix multiply unit implemented as a systolic array of cells are disclosed. The matrix multiply unit may include cells arranged in columns of the systolic array. Two chains of weight shift registers per column of the systolic array are in the matrix multiply unit. Each weight shift register is connected to only one chain and each cell is connected to only one weight shift register. A weight matrix register per cell is configured to store a weight input received from a weight shift register. A multiply unit is coupled to the weight matrix register and configured to multiply the weight input of the weight matrix register with a vector data input in order to obtain a multiplication result.

Abstract: To take advantage of the architecture of a systolic array tailored to perform sparse matrix multiplications, a weight matrix can be converted into a set of constrained fine-grained sparse weight matrices. The conversion process may include receiving a request to perform a matrix multiplication operation with a weight matrix, and determining that the weight matrix satisfies a sparsity condition to convert the weight matrix into a set of constrained fine-grained sparse weight matrices. The weight matrix can then be converted into a set of constrained fine-grained sparse weight matrices. Computer instructions can then be generated for an integrated circuit device to perform the requested matrix multiplication operation as a set of sparse matrix multiplication operations using the set of constrained fine-grained sparse weight matrices.

Abstract: Performing set operations using sparse matrix operations offered by a multi-core processing unit (such as a graphics processing unit). The set operation is converted into operand matrices, and sparse matrix operations, foregoing the use of hash tables. The input set is converted into a matrix, a matrix operation corresponding to the set operation is identified, and one or more operands of the set operation are also represented within a matrix. The matrix operation is then performed on these matrices to obtain an output matrix, which is then converted to an output set.

Abstract: An array circuit includes a plurality of vector-matrix multiplication (VMM) elements arranged in rows and columns. The VMM elements are configured to collectively perform multiplication of an input vector by a programmed input matrix to generate a plurality of output values that are representative of a result matrix that is the result of multiplication of the input vector and the input matrix. The VMM elements store states of the input matrix. Input voltages to the array are representative of elements of the input vector. A VMM element draws charge from a column read line based upon charging of a capacitor in the VMM. An integrator circuit connected to the column read line outputs a voltage that is indicative of a total charge drawn from the column read line by elements connected to the read line, which voltage is further indicative of an element of a result matrix.