Patents Examined by Telly Green
  • Patent number: 10286313
    Abstract: A virtual environment can use an absolute orientation framework. An absolute orientation framework in a virtual environment can be activated using an omnidirectional locomotion platform. An absolute orientation framework enables a user's avatar to move independently from the current viewpoint or camera position. The user's avatar can move in an absolute manner relative to a virtual environment map.
    Type: Grant
    Filed: March 19, 2015
    Date of Patent: May 14, 2019
    Assignee: Virtuix Holdings Inc.
    Inventors: Jan Goetgeluk, Ricardo Soza, Duane Bester, James Douglas Shuffield
  • Patent number: 10283444
    Abstract: Even when a stiffener is omitted, the semiconductor device which can prevent the generation of twist and distortion of a wiring substrate is obtained. As for a semiconductor device which has a wiring substrate, a semiconductor chip by which the flip chip bond was made to the wiring substrate, and a heat spreader adhered to the back surface of the semiconductor chip, and which omitted the stiffener for reinforcing a wiring substrate and maintaining the surface smoothness of a heat spreader, a wiring substrate has a plurality of insulating substrates in which a through hole whose diameter differs, respectively was formed, and each insulating substrate contains a glass cloth.
    Type: Grant
    Filed: October 27, 2017
    Date of Patent: May 7, 2019
    Assignee: Renesas Electronics Corporation
    Inventors: Eiji Hayashi, Kyo Go, Kozo Harada, Shinji Baba
  • Patent number: 10283407
    Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: May 7, 2019
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Cheng Chi, Ruilong Xie
  • Patent number: 10269744
    Abstract: A semiconductor device with thin redistribution layers is disclosed and may include forming a first redistribution layer on a dummy substrate, electrically coupling a semiconductor die to the first redistribution layer, and forming a first encapsulant layer on the redistribution layer and around the semiconductor die. The dummy substrate may be removed thereby exposing a second surface of the first redistribution layer. A dummy film may be temporarily affixed to the exposed second surface of the redistribution layer and a second encapsulant layer may be formed on the exposed top surface of the semiconductor die, a top surface and side edges of the first encapsulant layer, and side edges of the first redistribution layer. The dummy film may be removed to again expose the second surface of the first redistribution layer, and a second redistribution layer may be formed on the first redistribution layer and on the second encapsulant layer.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: April 23, 2019
    Assignee: Amkor Technology, Inc.
    Inventors: Dong Hoon Lee, Do Hyung Kim, Seung Chul Han
  • Patent number: 10262964
    Abstract: Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: April 16, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Hsiung Lu, Hsuan-Ting Kuo, Tsung-Yuan Yu, Hsien-Wei Chen, Ming-Da Cheng, Chung-Shi Liu
  • Patent number: 10249558
    Abstract: An electronic heat-dissipating substrate including: lead frames of wiring pattern shapes on a conductor plate; and an insulating member between the lead frames. A plate surface of the lead frames and a top surface of the insulating member form one continuous surface. The part arrangement surface is on both surfaces of the electronic part mounting heat-dissipating substrate, a reductant circuit which includes at least similar dual-system circuit is formed on the electronic part mounting heat-dissipating substrate, a first-system circuit of the dual-system circuit is formed on a first surface of the electronic part mounting heat-dissipating substrate, a second-system circuit of the dual-system circuit is formed on a second surface of the electronic part mounting heat-dissipating substrate, and the common lead frames used in a portion of a circuit wiring are used to the first surface and the second surface of the electronic part mounting heat-dissipating substrate.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: April 2, 2019
    Assignee: NSK LTD.
    Inventors: Shigeru Shimakawa, Takashi Sunaga, Takaaki Sekine, Teruyoshi Kogure, Ryoichi Suzuki
  • Patent number: 10242963
    Abstract: Provided is a manufacturing method of a sensor including the following steps. A mold having a cavity is provided. At least one chip is disposed in the cavity. The chip has an active surface and a back surface opposite to each other. The active surface faces toward a bottom surface of the cavity. A polymer material is filled in the cavity to cover the back surface of the chip. A heat treatment is performed, such that the polymer material is solidified to form a polymer substrate. A mold release treatment is performed to isolate the polymer substrate from the cavity. A plurality of conductive lines are formed on a first surface of the polymer substrate. The conductive lines are electrically connected with the chip.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: March 26, 2019
    Assignee: National Tsing Hua University
    Inventors: Yu-Lin Wang, Chen-Pin Hsu, Pei-Chi Chen
  • Patent number: 10236265
    Abstract: A semiconductor chip with different chip pads and a method for forming a semiconductor chip with different chip pads are disclosed. In some embodiments, the method comprises depositing a barrier layer over a chip front side, depositing a copper layer after depositing the barrier layer, and removing a part of the copper layer located outside a first chip pad region, wherein a remaining portion of the copper layer within the first chip pad region forms a surface layer of the chip pad. The method further comprises removing a part of the barrier layer located outside the first chip pad region.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: March 19, 2019
    Assignee: Infineon Technologies AG
    Inventors: Stefan Kramp, Marco Koitz
  • Patent number: 10237929
    Abstract: A solid-state light source (SSLS) with an integrated electronic modulator is described. A device can include a SSLS having an active p-n junction region is formed within the SSLS for electron-hole pair recombination and light emission. the active p-n junction region can include a n-type semiconductor layer, a p-type semiconductor layer and a light generating structure formed there between. A pair of current supply electrodes can be formed to receive a drive current from a current supply source that drives the SSLS. A field-effect transistor (FET) modulator can be monolithically integrated with the SSLS for modulation thereof. The FET modulator can receive a modulation voltage from a modulation voltage source. The modulation voltage includes voltage pulses having a pulse amplitude and polarity to turn on and off current flowing through the FET modulator. These voltage pulses enable the FET modulator to control the drive current supplied to the SSLS.
    Type: Grant
    Filed: April 20, 2017
    Date of Patent: March 19, 2019
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Grigory Simin, Michael Shur, Alexander Dobrinsky
  • Patent number: 10237933
    Abstract: A visible light communication LED having a spiral inductance coil and a circular core is provided, comprising a sapphire substrate provided with a positive electrode welding spot and a negative electrode welding spot, and a plurality of LED cores deposited on the sapphire substrate. The negative electrode of a former core is connected with the positive electrode of a latter core, and the positive electrode of the first core and the negative electrode of the last core are respectively connected to the positive electrode welding spot and the negative electrode welding spot on the substrate. According to the present invention, each of the LED cores is surrounded by a spiral inductance coil, and a pin of one end of the spiral inductance coil is connected via a connecting wire with the negative electrode of an adjacent LED core, while the other end is directly connected with the positive electrode of the LED core that is surrounded by the spiral inductance coil.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: March 19, 2019
    Assignee: SOUTH CHINA NORMAL UNIVERSITY
    Inventors: Huiqing Sun, Xian Yang, Zhiyou Guo, Yong Huang, Hongyong Huang, Jie Sun, Jing Huang, Zhuding Zhang, Yang Liu
  • Patent number: 10230004
    Abstract: The present disclosure provides a TFT, an array substrate and a fabricating method thereof and a display device. The TFT includes a gate, an active layer, a first electrode and a second electrode, the first electrode is arranged at one side of the active layer, the second electrode is arranged at the other side of the active layer, the first electrode, the active layer and the second electrode forms a stacked structure, the gate is arranged to surround the stacked structure, and the gate and the stacked structure are insulated and separated from each other. Under fixed occupation area, the conductive channel of the TFT of the present disclosure has increased width, so drain current in saturation region is increased without impacting aperture ratio of a display panel, which further optimizes performance of the TFT and the array substrate, and improves display effect of the display device.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: March 12, 2019
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Shaozhuan Wang
  • Patent number: 10224430
    Abstract: A method for manufacturing a semiconductor device includes forming a semiconductor layer on an insulating layer, epitaxially growing a first layer on the semiconductor layer, wherein the first layer has a first doping concentration, epitaxially growing a second layer on the semiconductor layer, wherein the second layer has a second doping concentration higher than the first doping concentration, forming a gate dielectric over an active region of the semiconductor layer, forming a gate electrode on the gate dielectric, and forming a plurality of source/drain contacts to the second layer, wherein the first and second layers comprise crystalline hydrogenated silicon (c-Si:H).
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: March 5, 2019
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Ghavam G. Shahidi, Marinus P. J. Hopstaken
  • Patent number: 10211053
    Abstract: Provided is a staircase-shaped connection structure of a three-dimensional semiconductor device. The device includes an electrode structure on a substrate, the electrode structure including an upper staircase region, a lower staircase region, and a buffer region therebetween. The electrode structure includes horizontal electrodes sequentially stacked on the substrate, the horizontal electrodes include a plurality of pad regions constituting a staircase structure of each of the upper and lower staircase regions, and the buffer region has a width that is larger than that of each of the pad regions.
    Type: Grant
    Filed: March 2, 2018
    Date of Patent: February 19, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Ik Oh, Daehyun Jang, Ha-Na Kim, Kyoungsub Shin
  • Patent number: 10211172
    Abstract: A surface mount device includes at least one semiconductor device including an exposed top metal, an encapsulation layer partially encapsulating the at least one semiconductor device, and at least one end-termination cap on the surface mount device resulting in an electrical connection from a first side of the surface mount device to a second side of the surface mount device. In implementations, one process for fabricating the surface mount device includes dicing a finished device wafer in a scribe-line region, applying tape to a first side of the finished device wafer, backgrinding a second side of the finished device wafer, encapsulating the second side of the finished device wafer with an encapsulation layer, singulating the finished device wafer, and forming at least one wrap-around connection from a first side of the surface mount device to a second side of the surface mount device.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: February 19, 2019
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Anuranjan Srivastava, Khanh Tran
  • Patent number: 10204945
    Abstract: Optical modules are made using customizable spacers to reduce variations in the focal lengths of the optical channels, to reduce the occurrence of tilt of the optical channels, and/or prevent adhesive from migrating to active portions of an image sensor.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: February 12, 2019
    Assignee: Heptagon Micro Optics Pte. Ltd.
    Inventors: Hartmut Rudmann, Jukka Alasirniö, Bojan Tesanovic, Tobias Senn, Devanraj Kupusamy, Alexander Bietsch
  • Patent number: 10199270
    Abstract: Interconnect structures and methods of fabricating an interconnect structure. First and second non-mandrel interconnects are formed in an interlayer dielectric layer. The first non-mandrel interconnect and the second non-mandrel interconnect have respective side surfaces that extend in a first direction. The connector interconnect extends in a second direction transverse to the first direction from the side surface of the first non-mandrel interconnect to the side surface of the second non-mandrel interconnect.
    Type: Grant
    Filed: May 25, 2017
    Date of Patent: February 5, 2019
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Colin Bombardier, Ming He, Vikrant Chauhan, Anbu Selvam KM Mahalingam, Keith Donegan
  • Patent number: 10199281
    Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
    Type: Grant
    Filed: February 7, 2018
    Date of Patent: February 5, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
  • Patent number: 10192818
    Abstract: An electronic part mounting heat-dissipating substrate which includes: a conductor plate which is formed on lead frames of wiring pattern shapes; and an insulating member which is provided between the lead frames of the wiring pattern shapes on the conductor plate; wherein a plate surface of a part arrangement surface of the conductor plate and a top surface of the insulating member at a side of the part arrangement surface form one continuous surface, wherein a plate surface of a back surface of the part arrangement surface of the conductor plate and a top surface of the insulating member at a side of the back surface at the part arrangement surface-side are formed in an identical plane, wherein the substrate is formed in a circular shape.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: January 29, 2019
    Assignee: NSK LTD.
    Inventors: Shigeru Simakawa, Takashi Sunaga, Takaaki Sekine, Teruyoshi Kogure, Ryoichi Suzuki
  • Patent number: 10193019
    Abstract: A light emitting diode chip including a substrate and a light emitting diode element layer is provided. The substrate has a growth surface and a plurality of microstructures on the growth surface. An area of the growth surface occupied by the microstructures is A1 and an area of the growth surface not occupied by the micro-structures is A2, such that A1 and A2 satisfy the relation of 0.1?A2/(A1+A2)?0.5. The light emitting diode element layer is disposed on the growth surface of the substrate.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: January 29, 2019
    Assignees: Everlight Electronics Co., Ltd., Southern Taiwan University of Science and Technology
    Inventor: Ming-Lun Lee
  • Patent number: 10192795
    Abstract: A semiconductor device including a power transistor is prevented from being broken. A cathode of a temperature sensing diode and a source of a power MOSFET are electrically coupled to each other so as to have the same potential. Such a characteristic point allows the temperature sensing diode to be disposed in a power MOSFET formation region without considering withstand voltage. This means that there is no need to provide an isolating structure that maintains a withstand voltage between the power MOSFET and the temperature sensing diode. Consequently, the power MOSFET and the temperature sensing diode can be closely disposed.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: January 29, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Kazuhisa Mori