Patents Examined by Telly Green
  • Light-emitting device
    Patent number: 9929350
    Abstract: A light-emitting element includes a light-emitting layer including a guest, an n-type host and a p-type host between a pair of electrodes, where the difference between the energy difference between a triplet excited state and a ground state of the n-type host (or p-type host) and the energy difference between a triplet excited state and a ground state of the guest is 0.15 eV or more. Alternatively, in such a light-emitting element, the LUMO level of the n-type host is higher than the LUMO level of the guest by 0.1 eV or more, or the HOMO level of the p-type host is lower than the HOMO level of the guest by 0.1 eV or more.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: March 27, 2018
    Assignee: Semiconducor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Satoshi Seo, Nobuharu Ohsawa, Satoko Shitagaki, Hideko Inoue, Hiroshi Kadoma, Harue Osaka, Kunihiko Suzuki, Yasuhiko Takemura
  • Wafer-level array cameras and methods for fabricating the same
    Patent number: 9923008
    Abstract: A wafer-level array camera includes (i) an image sensor wafer including an image sensor array, (ii) a spacer disposed on the image sensor wafer, and (iii) a lens wafer disposed on the spacer, wherein the lens wafer includes a lens array. A method for fabricating a plurality of wafer-level array cameras includes (i) disposing a lens wafer, including a plurality of lens arrays, on an image sensor wafer, including a plurality of image sensor arrays, to form a composite wafer and (ii) dicing the composite wafer to form the plurality of wafer-level array cameras, wherein each of the plurality of wafer-level array cameras includes a respective one of the plurality of lens arrays and a respective one of the plurality of image sensor arrays.
    Type: Grant
    Filed: April 9, 2014
    Date of Patent: March 20, 2018
    Assignee: OmniVision Technologies, Inc.
    Inventors: Raymond Wu, Robbert Emery
  • Thin-film transistor and method for fabricating the same, array substrate and method for fabricating the same, and display device
    Patent number: 9923067
    Abstract: A thin-film transistor (TFT) includes a gate electrode, a gate insulation layer, a source electrode, a drain electrode and an active layer arranged on a base substrate. The active layer includes an un-doped a-Si layer, a first doped a-Si layer and a second doped a-Si layer. One of the source electrode and the drain electrode is in contact with the first doped a-Si layer, and the other of the source electrode and the drain electrode is in contact with the second doped a-Si layer. The source electrode and the drain electrode are on different horizontal planes and spaced apart from each other, and the un-doped a-Si layer is positioned between the source electrode and the drain electrode.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: March 20, 2018
    Assignees: BOE Technology Group Co., Ltd., Beijing BOE Optoelectronics Technology Co., Ltd.
    Inventors: Wenbo Jiang, Shiyi Xie, Zhiying Bao
  • Method and system for calibrating a downhole imaging tool
    Patent number: 9921337
    Abstract: System and methods of generating calibrated downhole images of a subterranean formation (110) surrounding a wellbore (105). The method involves placing a pad at a distance from a highly conductive surface and measuring a current between return electrodes of the pad and the highly conductive surface. The current may be used to determine a theoretic impedance of the current path, and impedance amplitude and impedance phase may be calibrated using theoretical impedance phase and theoretical impedance amplitude. Multiple standoff calibrations and temperature variation calibrations may also be used.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 20, 2018
    Assignee: SCHLUMBERGER TECHNOLOGY CORPORATION
    Inventors: Richard Bloemenkamp, Laetitia Comparon, Andrew Hayman
  • Nanowire transistor structures with merged source/drain regions using auxiliary pillars
    Patent number: 9917200
    Abstract: A nanowire transistor structure is fabricated by using auxiliary epitaxial nucleation source/drain fin structures. The fin structures include semiconductor layers integral with nanowires that extend between the fin structures. Gate structures are formed between the fin structures such that the nanowires extend through the gate conductors. Following spacer formation and nanowire chop, source/drain regions are grown epitaxially between the gate structures.
    Type: Grant
    Filed: March 25, 2017
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Method of fabricating anti-fuse for silicon on insulator devices
    Patent number: 9917052
    Abstract: A method includes depositing a first hard mask layer on a first substrate; lithographically patterning and etching the first substrate to form a semiconductor link connected to an anode semiconductor region and a cathode semiconductor region; removing the first hard mask layer from the first substrate; depositing a second hard mask layer on the first substrate; patterning a photoresist on the first substrate and etching to form an opening in the semiconductor link; etching to remove portions of the second hard mask layer to expose a portion of a sidewall of the semiconductor link; removing the photoresist from the first substrate and the semiconductor link; and recessing the sidewalls of the semiconductor link forming first anti-fuse tip and second anti-fuse tip to form an anti-fuse with an opening between the first and second anti-fuse tips.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: March 13, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Juntao Li
  • Substrate features for inductive monitoring of conductive trench depth
    Patent number: 9911664
    Abstract: A substrate for use in fabrication of an integrated circuit has a layer with a plurality of conductive interconnects. The substrate includes a semiconductor body, a dielectric layer disposed over the semiconductor body, a plurality of conductive lines of a conductive material disposed in first trenches in the dielectric layer to provide the conductive interconnects, and a closed conductive loop structure of the conductive material disposed in second trenches in the dielectric layer. The closed conductive loop is not electrically connected to any of the conductive lines.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: March 6, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Wei Lu, Zhihong Wang, Wen-Chiang Tu, Zhefu Wang, Hassan G. Iravani, Boguslaw A. Swedek, Fred C. Redeker, William H. McClintock
  • Packaging mechanisms for dies with different sizes of connectors
    Patent number: 9911725
    Abstract: Embodiments of mechanisms for forming a die package with multiple packaged dies on a package substrate use an interconnect substrate to provide electrical connections between dies and the package substrate. The usage of the interconnect substrate enables cost reduction because it is cheaper to make than an interposer with through silicon vias (TSVs). The interconnect substrate also enables dies with different sizes of bump structures to be packaged in the same die package.
    Type: Grant
    Filed: May 3, 2017
    Date of Patent: March 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hua Chen, Chen-Shien Chen, Ching-Wen Hsiao
  • Apparatus and method for sensing
    Patent number: 9905720
    Abstract: An apparatus and method wherein the apparatus comprises: a sensing material configured to produce a non-random distribution of free charges in response to a parameter; an electric field sensor; a first conductive electrode comprising a first area overlapping the sensing material; an insulator provided between the first conductive electrode and the sensing material; a second electrode comprising a second area adjacent the electric field sensor; and a conductive interconnection between the first conductive electrode and the second conductive electrode.
    Type: Grant
    Filed: October 22, 2015
    Date of Patent: February 27, 2018
    Assignee: EMBERION OY
    Inventors: Alan Colli, Stefano Borini
  • Thin film transistor, array substrate and display device
    Patent number: 9905705
    Abstract: A thin film transistor, an array substrate and a display device are provided by the present disclosure. The thin film transistor is on a base substrate, a profile of a width edge of the channel includes an up-and-down curved section in a direction perpendicular to a surface of the base substrate.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: February 27, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Xiangchun Kong, Zhanfeng Cao, Wei Zhang, Bin Zhang, Xiaolong He, Jincheng Gao, Qi Yao, Zhengliang Li, Chuanxiang Xu
  • Electronic device, in particular for protection against overvoltages
    Patent number: 9899366
    Abstract: An electronic device is formed by a sequence of at least two thyristors coupled in series in a same conduction direction. Each thyristor has a gate of a first conductivity type. The gates of the first conductivity type for the thyristors in the sequence are coupled together in order to form a single control gate.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: February 20, 2018
    Assignee: STMicroelectronics SA
    Inventors: Johan Bourgeat, Jean Jimenez
  • Full-PDAF (phase detection autofocus) CMOS image sensor structures
    Patent number: 9893111
    Abstract: The present disclosure relates to an image sensor having autofocus function and associated methods. In some embodiments, the image sensor has first and second image sensing pixels arranged one next to another in a row. Each of the first and second image sensing pixels respectively have a left PD (phase detection) pixel including a left photodiode operably coupled to a left transfer gate, and a right PD pixel including a right photodiode operably coupled to a right transfer gate. The right transfer gate of the second image sensing pixel is a mirror image of the left transfer gate of the first image sensing pixel along a boundary line between the first and second image sensing pixels. The left transfer gate of the second image sensing pixel is a mirror image of the right transfer gate of the first image sensing pixel along the boundary line.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Keng-Yu Chou, Chun-Hao Chuang, Chien-Hsien Tseng, Dun-Nian Yaung, Wei-Chieh Chiang
  • Organic light-emitting display
    Patent number: 9893124
    Abstract: An organic light-emitting display including a substrate having a first pixel area to emit a light of a first color and a second pixel area to emit a light of a second color, a first anode disposed on the first pixel area and a second anode disposed on the second pixel area, a first emitting layer disposed on the first anode and a second emitting layer disposed on the second anode, the first emitting layer including a fluorescent light-emitting material and the second emitting layer including a first phosphorescent light-emitting material, a first buffer layer disposed on the first emitting layer and a second buffer layer disposed on the second emitting layer, the first buffer layer and the second buffer layer being formed of different materials, and a first cathode disposed on the first buffer layer and a second cathode disposed on the second buffer layer.
    Type: Grant
    Filed: October 9, 2014
    Date of Patent: February 13, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Ha Jin Song, Dal Ho Kim, Heun Seung Lee
  • Selective nitride outgassing process for MEMS cavity pressure control
    Patent number: 9884758
    Abstract: The present disclosure relates to a MEMS package having an outgassing element configured to adjust a pressure within a hermetically sealed cavity by inducing outgassing of into the cavity, and an associated method. In some embodiments, the method is performed by forming an outgassing element within a passivation layer over a CMOS substrate and forming an outgassing resistive layer to cover the outgassing element. The outgassing resistive layer is removed from over the outgassing element, and the MEMS substrate is bonded to a front side of the CMOS substrate to enclose a first MEMS device within a first cavity and a second MEMS device within a second cavity. After removing the outgassing resistive layer, the outgassing element releases a gas into the second cavity to increase a second pressure of the second cavity to be greater than a first pressure of the first cavity.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shyh-Wei Cheng, Hsi-Cheng Hsu, Hsin-Yu Chen, Ji-Hong Chiang, Jui-Chun Weng, Wei-Ding Wu, Yu-Jui Wu, Ching-Hsiang Hu, Ming-Tsung Chen
  • Optical modules including customizable spacers for focal length adjustment and/or reduction of tilt, and fabrication of the optical modules
    Patent number: 9887221
    Abstract: Optical modules are made using customizable spacers to reduce variations in the focal lengths of the optical channels, to reduce the occurrence of tilt of the optical channels, and/or prevent adhesive from migrating to active portions of an image sensor.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: February 6, 2018
    Assignee: Heptagon Micro Optics Pte. Ltd.
    Inventors: Hartmut Rudmann, Jukka Alasirniö, Bojan Tesanovic, Tobias Senn, Devanraj Kupusamy, Alexander Bietsch
  • Two-dimensional self-aligned super via integration on self-aligned gate contact
    Patent number: 9887133
    Abstract: Techniques relate to contacts for semiconductors. First gate contacts are formed on top of first gates, second gate contacts are on second gates, and terminal contacts are on silicide contacts. First gate contacts and terminal contacts are recessed to form a metal layer on top. Second gate contacts are recessed to be separately on each of the second gates. Filling material is formed on top of the recessed second gate contacts and metal layer. An upper layer is on top of the filling material. First metal vias are formed through filling and upper layers down to metal layer over first gate contacts. Second metal vias are formed through filling and upper layers down to metal layer over terminal contacts. Third metal vias are formed through filling and upper layers down to recessed second gate contacts over second gates. Third metal vias are taller than first.
    Type: Grant
    Filed: June 15, 2017
    Date of Patent: February 6, 2018
    Assignees: INTERNATIONAL BUSINESS MACHINES CORPORATION, GLOBALFOUNDRIES, INC.
    Inventors: Cheng Chi, Ruilong Xie
  • Method for forming a nanowire structure
    Patent number: 9882026
    Abstract: Embodiments of the invention describe a method for forming a nanowire structure on a substrate. According to one embodiment, the method includes a) depositing a first semiconductor layer on the substrate, b) etching the first semiconductor layer to form a patterned first semiconductor layer, c) forming a dielectric layer across the patterned first semiconductor layer, and d) depositing a second semiconductor layer on the patterned first semiconductor layer and on the dielectric layer. The method further includes e) repeating a)-d) at least once, f) following e), repeating a)-c) once, g) etching the patterned first semiconductor layers, the dielectric layers, and the second semiconductor layers to form a fin structure, and h) removing the patterned first semiconductor layers from the fin structure.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: January 30, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Kandabara N. Tapily, Genji Nakamura
  • Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions
    Patent number: 9882027
    Abstract: Confined epitaxial regions for semiconductor devices and methods of fabricating semiconductor devices having confined epitaxial regions are described. For example, a semiconductor structure includes a plurality of parallel semiconductor fins disposed above and continuous with a semiconductor substrate. An isolation structure is disposed above the semiconductor substrate and adjacent to lower portions of each of the plurality of parallel semiconductor fins. An upper portion of each of the plurality of parallel semiconductor fins protrudes above an uppermost surface of the isolation structure. Epitaxial source and drain regions are disposed in each of the plurality of parallel semiconductor fins adjacent to a channel region in the upper portion of the semiconductor fin. The epitaxial source and drain regions do not extend laterally over the isolation structure.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: January 30, 2018
    Assignee: Intel Corporation
    Inventors: Szuya S. Liao, Michael L. Hattendorf, Tahir Ghani
  • Method for manufacturing silicon carbide semiconductor apparatus, and energization test apparatus
    Patent number: 9874596
    Abstract: The present invention provides a method for manufacturing silicon carbide semiconductor apparatus including a testing step of testing a PN diode for the presence or absence of stacking faults in a relatively short time and an energization test apparatus. The present invention sets the temperature of a bipolar semiconductor element at 150° C. or higher and 230° C. or lower, causes a forward current having a current density of 120 [A/cm2] or more and 400 [A/cm2] or less to continuously flow through the bipolar semiconductor element, calculates, in a case where a forward resistance of the bipolar semiconductor element through which the forward current flows reaches a saturation state, the degree of change in the forward resistance, and determines whether the calculated degree of change is smaller than a threshold value.
    Type: Grant
    Filed: March 10, 2014
    Date of Patent: January 23, 2018
    Assignee: MITSUBISHI ELECTRIC CORPORATION
    Inventors: Shoyu Watanabe, Akihiro Koyama, Shigehisa Yamamoto, Yukiyasu Nakao, Kazuya Konishi
  • Semiconductor device with buried doped region and contact structure
    Patent number: 9876105
    Abstract: A semiconductor device includes a buried doped region at a first distance to a main surface of a semiconductor body. A contact structure extends from the main surface to the doped region. The contact structure includes a contact layer formed from a metal-semiconductor alloy that directly adjoins the doped region. The contact structure further includes a fill structure formed from a metal or a conductive metal compound. An insulator structure surrounds the contact structure in cross-sections parallel to the main surface.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: January 23, 2018
    Assignee: Infineon Technologies Dresden GmbH
    Inventors: Marko Lemke, Stefan Tegen, Rolf Weis