Patents Examined by Telly Green
  • Patent number: 10110312
    Abstract: A visible light communication emission device with improved response frequency is provided, comprising a substrate, wherein an inductance coil module is provided on the substrate, a LED chip matrix formed by series connection of a plurality of LED chips is provided on the inductance coil module, and the inductance coil module and the LED chip matrix are connected in series, wherein inductance value L of the inductance coil module is configured to be: L=1/(?2C), with C representing capacity in the device provided by LED chips and ? representing frequency, wherein the inductance coil module comprises more than one inductance coil whose composition materials from inside to outside are successively Cr, Al, Cr, Ti, and Ag.
    Type: Grant
    Filed: April 18, 2017
    Date of Patent: October 23, 2018
    Assignee: SOUTH CHINA NORMAL UNIVERSITY
    Inventors: Zhiyou Guo, Jie Sun, Jing Huang, Huiqing Shun, Hongyong Huang, Yong Huang, Xian Yang, Zhuding Zhang, Yang Liu, Min Guo, Shunyu Yao, Xinyan Yi, Xuancong Fang
  • Patent number: 10103262
    Abstract: A method of forming a semiconductor structure includes the following operations: (i) forming a feature comprising germanium over a substrate; (ii) removing a portion of the feature such that an interior portion of the feature is exposed; (iii) exposing a surface of the exposed interior portion to a surrounding containing oxygen; and (iv) treating the germanium oxide on the surface of the exposed interior portion with a liquid containing water.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei Hung, Chien-Feng Lin, Chia-Chiung Lo
  • Patent number: 10103147
    Abstract: Semiconductor devices and methods of forming the same include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: October 16, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Zhenxing Bi, Choonghyun Lee, Zheng Xu
  • Patent number: 10102996
    Abstract: A method for manufacturing a microelectronic semiconductor device comprising the steps of: forming a trench in a body, the trench having side walls, a opening, and a bottom; forming a sacrificial layer in the trench; forming a recess in the sacrificial layer; forming a restriction structure between the sacrificial layer and the opening of the trench, defining a through hole for access to the sacrificial layer; completely removing the sacrificial layer through said through hole; and depositing a metal layer over the body, thus closing the opening of the trench and forming an electron-emission cathode tip.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 16, 2018
    Assignee: STMICROELECTRONICS S.R.L.
    Inventors: Antonino Fiumara, Marcello Frazzica, Giuseppe Digrazia
  • Patent number: 10103122
    Abstract: Hybrid bonding systems and methods for semiconductor wafers are disclosed. In one embodiment, a hybrid bonding system for semiconductor wafers includes a chamber and a plurality of sub-chambers disposed within the chamber. A robotics handler is disposed within the chamber that is adapted to move a plurality of semiconductor wafers within the chamber between the plurality of sub-chambers. The plurality of sub-chambers includes a first sub-chamber adapted to remove a protection layer from the plurality of semiconductor wafers, and a second sub-chamber adapted to activate top surfaces of the plurality of semiconductor wafers prior to hybrid bonding the plurality of semiconductor wafers together. The plurality of sub-chambers also includes a third sub-chamber adapted to align the plurality of semiconductor wafers and hybrid bond the plurality of semiconductor wafers together.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: October 16, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Ping-Yin Liu, Shih-Wei Lin, Xin-Hua Huang, Lan-Lin Chao, Chia-Shiung Tsai
  • Patent number: 10096709
    Abstract: Aspect ratio trapping (ART) approaches for fabricating vertical semiconductor devices and vertical semiconductor devices fabricated there from are described. For example, a semiconductor device includes a substrate with an uppermost surface having a first lattice constant. A first source/drain region is disposed on the uppermost surface of the substrate and has a second, different, lattice constant. A vertical channel region is disposed on the first source/drain region. A second source/drain region is disposed on the vertical channel region. A gate stack is disposed on and completely surrounds a portion of the vertical channel region.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: October 9, 2018
    Assignee: Intel Corporation
    Inventors: Van H. Le, Benjamin Chu-Kung, Gilbert Dewey, Jack T. Kavalieros, Ravi Pillarisetty, Willy Rachmady, Marko Radosavljevic, Matthew V. Metz, Niloy Mukherjee, Robert S. Chau
  • Patent number: 10096571
    Abstract: A method includes bonding a die to a substrate, where the substrate has a first redistribution structure, the die has a second redistribution structure, and the first redistribution structure is bonded to the second redistribution structure. A first isolation material is formed over the substrate and around the die. A first conductive via is formed, extending from a first surface of the substrate, where the first surface is opposite the second redistribution structure, the first conductive via contacting a first conductive element in the second redistribution structure. Forming the first conductive via includes patterning an opening in the substrate, extending the opening to expose the first conductive element, where extending the opening includes using a portion of a second conductive element in the first redistribution structure as an etch mask, and filling the opening with a conductive material.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: October 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Sung-Feng Yeh
  • Patent number: 10090459
    Abstract: A magnetoresistive element includes a storage layer as a ferromagnetic layer which has magnetic anisotropy perpendicular to film planes, and in which a magnetization direction is variable, a reference layer as a ferromagnetic layer which has magnetic anisotropy perpendicular to film planes, and in which a magnetization direction is invariable, a tunnel barrier layer as a nonmagnetic layer formed between the storage layer and the reference layer, and a first underlayer formed on a side of the storage layer, which is opposite to a side facing the tunnel barrier layer, and containing amorphous W.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: October 2, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Daisuke Watanabe, Youngmin Eeh, Kazuya Sawada, Koji Ueda, Toshihiko Nagase
  • Patent number: 10074569
    Abstract: Semiconductor structures and methods of forming such structures are disclosed. In an embodiment, the semiconductor structure comprises a substrate, a dielectric layer, and a plurality of gates, including a first gate and a pair of adjacent gates. The method comprises forming gate caps on the adjacent gates, including etching portions of the gate electrodes in the adjacent gates to recess the gate electrodes therein, and forming the caps above the recessed gate electrodes. Conductive metal trenches are formed in the dielectric layer, on the sides of the first gate; and after forming the trenches, a contact is formed over the gate electrode of the first gate and over and on one of the conductive trenches. In embodiments, the contact is a gate contact, and in other embodiments, the contact is a non-gate contact.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: September 11, 2018
    Assignee: International Business Machines Corporation
    Inventors: Injo Ok, Balasubramanian Pranatharthiharan, Soon-Cheon Seo, Charan V. Surisetty
  • Patent number: 10074671
    Abstract: A display panel includes a substrate including a display area, a peripheral area and a buffer area disposed between the display area and the peripheral area. The display panel further includes a switching element disposed in the display area. The switching element includes an active pattern, a gate electrode overlapping the active pattern, a source electrode connecting with the active pattern, and a drain electrode spaced apart from the source electrode. The display panel further includes a power supply line disposed in the peripheral area and disposed on a same layer as the source electrode and the drain electrode. The display panel additionally includes a power connecting line disposed in the buffer area and connecting the switching element to the power supply line. The display panel further includes a dummy active pattern disposed in the buffer area and overlapping the power connecting line.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 11, 2018
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Chang-Soo Pyon, Ju-Hee Hyeon
  • Patent number: 10069007
    Abstract: A technique relates to semiconductors. A bottom terminal of a transistor and bottom plate of a capacitor are positioned on the substrate. A spacer is arranged on the bottom terminal of the transistor. A transistor channel region extends vertically from the bottom terminal through the spacer to contact a top terminal of the transistor. A capacitor channel region extends vertically from the bottom plate to contact a top plate of the capacitor. A first gate stack is arranged along sidewalls of the transistor channel region and is in contact with the spacer. A second gate stack is arranged along sidewalls of the capacitor channel region and is disposed on the bottom plate. A distance from a bottom of the first gate stack to a top of the bottom terminal is greater than a distance from a bottom of the second gate stack to a top of the bottom plate.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 4, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Brent A. Anderson
  • Patent number: 10049983
    Abstract: A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cha-Hsin Chao, Chih-Hao Chen, Hsin-Yi Tsai
  • Patent number: 10050074
    Abstract: A semiconductor device including a semiconductor substrate having oppositely facing first and second surfaces, the first surface being an active surface and provided with an electronic element thereon, a pad electrode to be connected to the electronic element in a peripheral portion of the electronic element on the active surface, a first opening extending from the second surface toward the pad electrode so as not to reach the first surface of the semiconductor substrate, a second opening formed to reach the pad electrode from a bottom surface of the first opening and having a diameter smaller than that of the first opening, an insulating layer formed to cover sidewall surfaces of the first opening and the second opening, and a conductive layer formed, inside of the insulating layer, to cover at least an inner wall surface of the insulating layer and a bottom surface of the second opening.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: August 14, 2018
    Assignee: Sony Corporation
    Inventors: Yoshihiro Nabe, Hiroshi Asami, Yuji Takaoka, Yoshimichi Harada
  • Patent number: 10043796
    Abstract: A device includes a substrate, a first nanowire field effect transistor (FET), and a second nanowire FET positioned between the substrate and the first nanowire FET. The device also includes a first nanowire electrically coupled to the first nanowire FET and to the second nanowire FET.
    Type: Grant
    Filed: April 12, 2016
    Date of Patent: August 7, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Vladimir Machkaoutsan, Stanley Seungchul Song, Mustafa Badaroglu, John Jianhong Zhu, Junjing Bao, Jeffrey Junhao Xu, Da Yang, Matthew Michael Nowak, Choh Fei Yeap
  • Patent number: 10043683
    Abstract: A chuck, a system including a chuck and a method for making a semiconductor device are disclosed. In one embodiment the chuck includes a first conductive region configured to be capacitively coupled to a first RF power generator, a second conductive region configured to be capacitively coupled to a second RF power generator and an insulation region that electrically insulates the first conductive region from the second conductive region.
    Type: Grant
    Filed: November 22, 2016
    Date of Patent: August 7, 2018
    Assignee: Infineon Technologies AG
    Inventor: Manfred Engelhardt
  • Patent number: 10037943
    Abstract: A method for fabricating a metal gate transistor includes forming a dummy gate structure surrounded by a first dielectric layer on a semiconductor substrate and a source/drain region in the semiconductor substrate on each side of the dummy gate structure. The top surface of the dummy gate structure is leveled with the top surface of the first dielectric layer. The method then includes forming an etch stop sidewall in the first dielectric layer on each side of the dummy gate structure, forming a first trench by removing the dummy gate structure, and forming a metal gate structure to partially fill the first trench. The top portion of the first trench becomes a second trench. Further, the method also includes forming an etch stop layer by filling the second trench, and then forming a contact plug in the first dielectric layer to electrically connect to each source/drain region.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: July 31, 2018
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jie Zhao
  • Patent number: 10037997
    Abstract: A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.
    Type: Grant
    Filed: March 7, 2018
    Date of Patent: July 31, 2018
    Assignee: SK Hynix Inc.
    Inventors: Dong-Kyun Kang, Ho-Jin Cho
  • Patent number: 10032715
    Abstract: An interconnection component includes a semiconductor material layer having a first surface and a second surface opposite the first surface and spaced apart in a first direction. At least two metalized vias extend through the semiconductor material layer. A first pair of the at least two metalized vias are spaced apart from each other in a second direction orthogonal to the first direction. A first insulating via in the semiconductor layer extends from the first surface toward the second surface. The insulating via is positioned such that a geometric center of the insulating via is between two planes that are orthogonal to the second direction and that pass through each of the first pair of the at least two metalized vias. A dielectric material at least partially fills the first insulating via or at least partially encloses a void in the insulating via.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: July 24, 2018
    Assignee: Invensas Corporation
    Inventors: Cyprian Emeka Uzoh, Zhuowen Sun
  • Patent number: 10020284
    Abstract: A device includes a spacer, which includes a recess extending from a top surface of the spacer into the spacer, and a conductive feature including a first portion and a second portion continuously connected to the first portion. The first portion extends into the recess. The second portion is on the top surface of the spacer. A die is attached to the spacer, and a lower portion of the first die extends into the recess.
    Type: Grant
    Filed: September 28, 2015
    Date of Patent: July 10, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Ru Chang, Chung-Kai Wang, Ming-Che Wu
  • Patent number: 10014417
    Abstract: A solid state imaging apparatus includes an insulation structure formed of an insulation substance penetrating through at least a silicon layer at a light receiving surface side, the insulation structure having a forward tapered shape where a top diameter at an upper portion of the light receiving surface side of the silicon layer is greater than a bottom diameter at a bottom portion of the silicon layer. Also, there are provided a method of producing the solid state imaging apparatus and an electronic device including the solid state imaging apparatus.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: July 3, 2018
    Assignee: Sony Corporation
    Inventors: Kyohei Mizuta, Tomokazu Ohchi, Yohei Chiba