Patents Examined by Telly Green
  • Patent number: 10192941
    Abstract: The display device includes a first substrate having flexibility and including pixels arranged in matrix form in a first direction and a second direction, the first direction and second direction mutually intersecting each other, a transistor layer arranged above the first substrate and including at least one transistor arranged in each of the pixels, an inorganic insulation film formed continuously across the pixels in the second direction, and a plurality of aperture parts extending in the second direction and arranged between two transistors arranged in two of the plurality of pixels adjacent in the first direction, a plurality of first groups of wiring extending in the first direction and connected to each of the pixels arranged in the first direction, and a plurality of second groups of wiring extending in the second direction and connected to each of the pixels arranged in the second direction.
    Type: Grant
    Filed: November 28, 2016
    Date of Patent: January 29, 2019
    Assignee: Japan Display Inc.
    Inventor: Toshihiro Sato
  • Patent number: 10192828
    Abstract: A metal gate transistor is provided. The metal gate transistor includes a semiconductor substrate; a metal gate structure formed on the semiconductor substrate; source/drain regions formed in the semiconductor substrate on sides of the metal gate structure; an etch stop layer formed on a top surface of the metal gate structure with a top surface leveled with a top surface of the first dielectric layer; an etch stop sidewall formed on each side of the metal gate structure with a top surface leveled with the top surface of the first dielectric layer; and a contact plug formed in the first dielectric layer to electrically connect to each source/drain region formed in the semiconductor substrate.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: January 29, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Jie Zhao
  • Patent number: 10186427
    Abstract: A substrate treating apparatus and a method of treating a substrate, the apparatus including a substrate treater that treats a substrate using a chemical solution, the chemical solution including a phosphoric acid aqueous solution and a silicon compound; and a chemical solution supplier that supplies the chemical solution to the substrate treating unit, wherein the chemical solution supplier includes a concentration measurer that measures concentrations of the chemical solutions, the concentration measurer including a first concentration measurer that measures a water concentration of the chemical solution; and a second concentration measurer that measures a silicon concentration of the chemical solution.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: January 22, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyoung Hwan Kim, Ingi Kim, Mihyun Park, Young-Hoo Kim, Ui-soon Park, Jung-Min Oh, Kuntack Lee, Hyosan Lee
  • Patent number: 10181525
    Abstract: According to embodiments of the inventive concept, a gate electrode is formed on a substrate, and a first spacer, a second spacer, and a third spacer are sequentially formed on a sidewall of the gate electrode. The substrate is etched to form a recess region. A compressive stress pattern is formed in the recess region. A protective spacer is formed on a sidewall of the third spacer. When the recess region is formed, a lower portion of the second spacer is removed to form a gap region between the first and third spacers. The protective spacer fills the gap region.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 15, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Donghyun Roh, Pankwi Park, Dongsuk Shin, Chulwoong Lee, Nae-in Lee
  • Patent number: 10171007
    Abstract: A method includes providing a substrate having a first sacrificial oxide region, the substrate comprising a first interconnect layer, the first interconnect layer comprising the first sacrificial oxide region. The method further includes covering the first sacrificial oxide region with a first porous layer being permeable to a vapor hydrofluoric acid (HF) etchant and selectively etching the first sacrificial oxide region through the first porous layer using the vapor HF etchant.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 1, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Greja Johanna Adriana Maria Verheijden, Roel Daamen, Gerhard Koops
  • Patent number: 10170428
    Abstract: Embodiments are generally directed to cavity generation for an embedded interconnect bridge utilizing a temporary structure. An embodiment of a package includes a substrate; a silicon interconnect bridge including a plurality of interconnections, the interconnect bridge being embedded in the substrate; and a plurality of contacts on a surface of the substrate, the plurality of contacts being coupled with the plurality of interconnections of the interconnect bridge. The interconnect bridge is bonded in a cavity in the substrate, the cavity being formed by removal of at least one temporary structure from the substrate.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: January 1, 2019
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli
  • Patent number: 10170637
    Abstract: A semiconductor device including a plurality of suspended nanowires and a gate structure that is present on a channel region portion of the plurality of suspended nanowires. The gate structure includes a uniform length extending from an upper surface of the gate structure to the base of the gate structure. A dielectric spacer having a graded composition is present in direct contact with the gate structure. The dielectric spacer having a uniform length extending from an upper surface of the gate structure to the base of the gate structure. Source and drain regions are present on source and drain region portions of the plurality of suspended nanowires.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Pouya Hashemi, Ali Khakifirooz, Alexander Reznicek
  • Patent number: 10157882
    Abstract: Disclosed herein is a package comprising a first redistribution layer (RDL) disposed on a first side of a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate, wherein the first RDL is bonded to the second RDL. First conductive elements are disposed in the first RDL and the second RDL. First vias extend from one or more of the first conductive elements through the first semiconductor substrate to a second side of the first semiconductor substrate opposite the first side. First spacers are interposed between the first semiconductor substrate and the first vias and each extend from a respective one of the first conductive elements through the first semiconductor substrate.
    Type: Grant
    Filed: September 5, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Ming-Fa Chen, Wen-Ching Tsai, Sung-Feng Yeh
  • Patent number: 10157923
    Abstract: Methods of forming semiconductor devices include forming vertical semiconductor channels on a bottom source/drain layer in a first-type region and a second-type region. A gate dielectric layer is formed on sidewalls of the vertical semiconductor channels. A first-type work function layer is formed in the first-type region. A second-type work function layer is formed in both the first-type region and the second-type region. A thickness matching layer is formed in the second-type region such that a stack of layers in the first-type region has a same thickness as a stack of layers in the second-type region. Top source/drain regions are formed on a top portion of the vertical channels.
    Type: Grant
    Filed: November 8, 2017
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Zhenxing Bi, Choonghyun Lee, Zheng Xu
  • Patent number: 10154584
    Abstract: A method of producing a non-planar conforming circuit on a non-planar surface includes creating a first set of conforming layers. The first set of conforming layers is created by applying an oxide dielectric layer to the surface, applying a conductive material layer to the oxide dielectric layer, applying a resist layer to the conductive material layer, patterning the resist layer according to a desired circuit layout, etching the surface to remove exposed conductive material, and stripping the resist layer. The process may be repeated to form multiple layers of conforming circuits with electrical connections between layers formed by blind microvias. The resulting set of conforming layers can be sealed.
    Type: Grant
    Filed: July 28, 2016
    Date of Patent: December 11, 2018
    Assignee: Lockheed Martin Corporation
    Inventors: Stephen Gonya, James Sean Eiche, James Patterson, Kenneth R. Twigg
  • Patent number: 10153284
    Abstract: A semiconductor device includes a substrate comprising a trench; a gate dielectric layer formed over a surface of the trench; a gate electrode positioned at a level lower than a top surface of the substrate, and comprising a lower buried portion embedded in a lower portion of the trench over the gate dielectric layer and an upper buried portion positioned over the lower buried portion; and a dielectric work function adjusting liner positioned between the lower buried portion and the gate dielectric layer; and a dipole formed between the dielectric work function adjusting liner and the gate dielectric layer.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: December 11, 2018
    Assignee: SK Hynix Inc.
    Inventors: Dong-Kyun Kang, Ho-Jin Cho
  • Patent number: 10153395
    Abstract: Semiconductor structures and methods for forming those semiconductor structures are disclosed. For example, a p-type or n-type semiconductor structure is disclosed. The semiconductor structure has a polar crystal structure with a growth axis that is substantially parallel to a spontaneous polarization axis of the polar crystal structure. The semiconductor structure changes in composition from a wider band gap (WBG) material to a narrower band gap (NBG) material or from a NBG material to a WBG material along the growth axis to induce p-type or n-type conductivity.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: December 11, 2018
    Assignee: Silanna UV Technologies Pte Ltd
    Inventors: Petar Atanackovic, Matthew Godfrey
  • Patent number: 10141452
    Abstract: A semiconductor device includes a first insulating layer over a substrate, a first metal oxide layer over the first insulating layer, an oxide semiconductor layer over the first metal oxide layer, a second metal oxide layer over the oxide semiconductor layer, a gate insulating layer over the second metal oxide layer, a second insulating layer over the second metal oxide layer, and a gate electrode layer over the gate insulating layer. The gate insulating layer includes a region in contact with a side surface of the gate electrode layer. The second insulating layer includes a region in contact with the gate insulating layer. The oxide semiconductor layer includes first to third regions. The first region includes a region overlapping with the gate electrode layer. The second region, which is between the first and third regions, includes a region overlapping with the gate insulating layer or the second insulating layer.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: November 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Daigo Ito, Daisuke Matsubayashi, Masaharu Nagai, Yoshiaki Yamamoto, Takashi Hamada, Yutaka Okazaki, Shinya Sasagawa, Motomu Kurata, Naoto Yamade
  • Patent number: 10135027
    Abstract: A light-emitting element display device includes: a display area which has an organic insulating layer that is made of an organic insulating material; a peripheral circuit area which is disposed around the display area and which has the organic insulating layer; and a blocking area that is formed between the display area and the peripheral circuit area. The blocking area includes: a first blocking area configured by only one or a plurality of inorganic material layers between an insulating base substrate and an electrode layer which covers the display area and is formed continuously from the display area, and which configures one of two electrodes for allowing the light emitting area to emit the light; and a second blocking area including a plurality of layers configuring the first blocking area, and a light emitting organic layer.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 20, 2018
    Assignee: Japan Display Inc.
    Inventor: Masamitsu Furuie
  • Patent number: 10128389
    Abstract: An ultraviolet light sensor and method of manufacturing thereof are disclosed. The ultraviolet light sensor includes Group-III Nitride layers adjacent to a silicon wafer with one of the layers at least partially exposed such that a surface thereof can receive UV light to be detected. The Group-III Nitride layers include a p-type layer and an n-type layer, with p/n junctions therebetween forming at least one diode. Conductive contacts are arranged to conduct electrical current through the sensor as a function of ultraviolet light received at the outer Group-III Nitride layer. The Group-III Nitride layers may be formed from, e.g., GaN, InGaN, AlGaN, or InAlN. The sensor may include a buffer layer between one of the Group-III Nitride layers and the silicon wafer. By utilizing silicon as the substrate on which the UV sensor diode is formed, a UV sensor can be produced that is small, efficient, cost-effective, and compatible with other semiconductor circuits and processes.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: November 13, 2018
    Assignee: ROSESTREET LABS, LLC
    Inventors: Robert Forcier, Wladyslaw Walukiewicz
  • Patent number: 10123410
    Abstract: A method of producing a non-planar conforming circuit on a non-planar surface includes creating a first set of conforming layers. The first set of conforming layers is created by applying an oxide dielectric layer to the surface, applying a conductive material layer to the oxide dielectric layer, applying a resist layer to the conductive material layer, patterning the resist layer according to a desired circuit layout, etching the surface to remove exposed conductive material, and stripping the resist layer. The process may be repeated to form multiple layers of conforming circuits with electrical connections between layers formed by blind microvias. The resulting set of conforming layers can be sealed.
    Type: Grant
    Filed: October 10, 2014
    Date of Patent: November 6, 2018
    Assignee: Lockheed Martin Corporation
    Inventors: Stephen Gonya, James Sean Eiche, James Patterson, Kenneth R. Twigg
  • Patent number: 10121840
    Abstract: The disclosure discloses an active matrix organic light emitting diode panel and a method for manufacturing the same. The active matrix organic light emitting diode panel includes: a substrate, an organic film formed on the substrate, and a plurality of red, green and blue organic light emitting diodes formed on the organic film. A first recess or a first protrusion is formed in the organic film in a region corresponding to the blue organic light emitting diode. The blue organic light emitting diode is formed on the first recess or first protrusion, and a contact area of the blue organic light emitting diode with the organic film is S r ? ? 0 Lifetime b ? ? 0 Lifetime r ? ? 0 n times as great as a contact area of the red organic light emitting film with the organic film, wherein n is a value ranging from 1.4 to 1.6.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: November 6, 2018
    Assignee: SHANGHAI TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Zhiyong Xiong, Bengang Zhao
  • Patent number: 10115657
    Abstract: Devices, systems, and methods for dissipating heat generated from an electrical current carrying device are provided herein. The disclosed concept provides a dielectric heat path device that assists in heat dissipation of an electrical current carrying device by transferring heat from one end of the device to another. The disclosed concept also provides systems that communicate heat generated by an electrical device to a thermally grounded secondary device through a dielectric heat path device to dissipate heat.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: October 30, 2018
    Assignee: EATON INTELLIGENT POWER LIMITED
    Inventors: Tony Ray Benson, Peter J. Fritz
  • Patent number: 10109715
    Abstract: A semiconductor device according to an embodiment includes: a substrate having a first plane and a second plane provided on the opposite side of the first plane; a first nitride semiconductor layer provided on the first plane; source electrodes provided on the first nitride semiconductor layer; drain electrodes provided on the first nitride semiconductor layer, each of the drain electrodes provided between the source electrodes; gate electrodes provided on the first nitride semiconductor layer, each of the gate electrodes provided between each of the source electrodes and each of the drain electrodes; a first wire provided on the second plane and electrically connected to the source electrodes; a second wire electrically connected to the drain electrodes; a third wire provided on the second plane and electrically connected to the gate electrodes; and an insulating interlayer provided between the first nitride semiconductor layer and the second wire.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: October 23, 2018
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yosuke Kajiwara, Kentaro Ikeda, Hisashi Saito, Masahiko Kuraguchi
  • Patent number: 10109710
    Abstract: A semiconductor device having a channel region that is formed in a germanium layer and has a first conductive type, and a source region and a drain region that are formed in the germanium layer and have a second conductive type different from the first conductive type, wherein an oxygen concentration in the channel region is less than an oxygen concentration in a junction interface between at least one of the source region and the drain region and a region that surrounds the at least one of the source region and the drain region and has the first conductive type.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: October 23, 2018
    Assignee: Japan Science and Technology Agency
    Inventors: Akira Toriumi, Choong-hyun Lee, Tomonori Nishimura