Abstract: Aspects of performing power management operations in a distributed computer system are described. In some aspects, predicted demand data is generated for clients executed in a cluster of host computers. The predicted demand data is based on observed resource demands of the clients. A power management setting for a time period is determined. The power management setting is based on the predicted demand data. A host computer is caused to power-down or power-up in order to apply the power management setting.

Abstract: A method of controlling a computing device including a physical battery and at least one group of applications executable on hardware resources of the computing device, each group including one or more applications. The method comprises controlling each group of applications based on a state of a respective virtual battery associated each group of applications, each virtual battery having a respective virtual capacity corresponding to a defined portion of a capacity of the physical battery and a respective virtual battery reserve representing an amount of energy that is available for use by the group of applications associated with the virtual battery.

Abstract: According to one general aspect, an apparatus may include a register circuit and an instruction scheduler circuit. The register circuit may include a plurality of physical registers that are partitioned into at least a common portion that is associated with a predefined plurality of instructions, and a shared portion, and a plurality of write ports, wherein each portion is associated with at least one respective write port. The instruction scheduler circuit configured to determine an instruction, and rename an architectural register associated with the instruction to a physical register. Wherein the portion including the physical register is selected based, at least in part, upon a characteristic of the current instruction.

Abstract: A processor is described that includes a quick signal path from an input of the processor to logic circuitry within the processor. The input is to receive a fast throttle down signal. The logic circuitry is to throttle down a rate at which the processor issues instructions for execution in response to the fast throttle down signal. The quick signal path is to impose practicably minimal propagation delay of the fast throttle down signal within the processor.

Abstract: Embodiments are disclosed for methods and systems for selectively initializing elements of an operating system of a computing device. In some embodiments, a method of selectively loading classes during an initialization of an operating system of a computing device comprises starting a service-loading process, loading critical services via the service-loading process, and launching a human-machine interface. The method may further include launching a last-used application via the human-machine interface, and launching remaining services responsive to requests for use of the remaining services.

Abstract: A method for adjusting a pull resistor on a contact terminal of an electronic module arranged on a printed circuit board, in particular an ASIC, after initiating a restart of the electronic module which, during a run-up process, moves the electronic module from a switched-off state into a switched-on state, wherein after initiating a restart during the run-up process from a partial circuit arranged on the electronic module and operationally ready during the run-up process, adjustment information relating to a desired adjustment of the pull resistor is retrieved from a storage unit arranged on the printed circuit board outside of the electronic module and transmitted via a contact line between the electronic module and the storage unit, where the run-up process of the electronic module is only completed after successful adjustment of the respective pull resistor based on basis the retrieved adjustment information.

Abstract: An information processing device includes: a receiver that compares a serial input signal to a threshold value and outputs reception data; an extraction circuit that extracts a clock superimposed on the reception data from the reception data; a measurement circuit that measures a pulse width of the reception data based on the clock; a counter that measures an elongation and a shortening of the pulse width; and an adjustment circuit that increases the threshold value when the elongation of the pulse width is larger than a reference value, and reduces the threshold value when the shortening of the pulse width is larger than the reference value.

Abstract: A method of a storage area network (SAN) includes storing and communicating data received from a server at a host bus adapter via a bus controller of the adapter. In a case where the data is associated with an address corresponding to a default boot logical unit (LUN) of a non-volatile memory (NVM) of the adapter, the data is stored in the NVM. In a case where the data is not associated with an address corresponding to a boot LUN of the NVM, the data is communicated over the SAN. During power up of the adapter, in a case where it is determined that the NVM includes an image of an operating system, the adapter uses the bus controller to provide the server with information to select the NVM as a boot LUN for booting the operating system.

Abstract: An apparatus includes a communication interface, a controller, and a power section. The communication interface is configured to receive power from an external host to the apparatus. The controller is configured to limit a current drawn by the communication interface to a predetermined value when the apparatus is powered through the external host. The power section is configured to generate a first voltage from a portion of the limited current drawn by the communication interface. The first voltage powers a data storage circuitry. The power section is further configured to store electrical charges received from another portion of the limited current drawn by the communication interface. The power section is further configured to generate a second voltage from the stored electrical charges in response to a signal from the controller. The second voltage supplements the first voltage during high power events by the data storage circuitry.

Abstract: A computing device is associated with a circuit for sharing and distributing backup power. During normal operating conditions, a main bus bar provides power to each computing device in a rack via a main power bus of the corresponding circuit. In the event of an AC power outage, the main power bus is deactivated and a backup power path of the circuit is activated. Backup power is provided to the device from a battery of the circuit via the backup power path. A shared power path is also activated in the circuit such that backup power may be provided from the battery to the main bus bar. By providing backup power to the main bus bar, the other computing devices in the rack that do not have sufficient backup power may receive backup power from the main bus bar until AC power is restored.

Abstract: One embodiment describes a Josephson transmission line (JTL) system. The system includes a plurality of JTL stages that are arranged in series. The system also includes a clock transformer comprising a primary inductor configured to propagate an AC clock signal and a secondary inductor arranged in a series loop with at least two of the plurality of JTL stages. The clock transformer can be configured to propagate a single flux quantum (SFQ) pulse to set a respective one of the plurality of JTL stages in response to a first phase of the AC clock signal and to reset the respective one of the plurality of JTL stages in response to a second phase of the AC clock signal that is opposite the first phase.

Abstract: In an approach for selecting a boot-up path in a multi-node server, a processor receives a first set of computing capability data for a first boot-up path of a server and a second set of computing capability data for a second boot-up path of the server. A processor compares the first set of computing capability data to the second set of computing capability data. A processor determines that the first boot-up path has greater computing capabilities than the second boot-up path based on the comparison. Responsive to determining the first boot-up path has greater computing capabilities, a processor boots-up the server using the first boot-up path.

Abstract: An example disclosed herein is a non-volatile storage medium including instructions relating to control of power that, when executed by a processor, cause the processor to monitor a supply of power to a regulator, decouple supply of power to the regulator when the monitored supply of power is below a predetermined level, couple a power pack to the regulator to supply power to the regulator when the monitored supply of power is below the predetermined level, and generate an Advanced Configuration and Power Interface (ACPI) G1 Sleeping state signal when the monitored supply of power is below the predetermined level.

Abstract: In one embodiment, a processor includes: a plurality of cores; a power controller including a logic to autonomously demote a first request for at least one core of the plurality of cores to enter a first low power state, to cause the at least one core to enter a second low power state, the first low power state a deeper low power state than the second low power state; and an interface to receive an input from a system software, the input including at least one demotion control parameter, where the logic is to autonomously demote the first request based at least in part on the at least one demotion control parameter. Other embodiments are described and claimed.

Abstract: A method includes a power supply system receiving a first request for a first quantity of power for a first time period from a first unit. The system generates a first quote based on an available power generation capacity, environmental factors and a forecasted level of power consumption. The system transmits the first quote to the first unit. The system receives a second request for a second quantity of power for a second time period. The system generates a second quote based on the same factors as the first quote. The system transmits the second quote to the second unit. The value of the first quote and the value of the second quote are set to discourage demand in a first mode and to encourage demand in a second mode to maximize efficient operating levels of the power generation sources in both the first mode and the second mode.

Abstract: A system may include a driver circuit configured to receive a clock signal. The system may also include a first tuned circuit and a second tuned circuit. The first tuned circuit and the driver circuit may be collectively tuned according to a first frequency range. The first tuned circuit may be configured to be active when a rate of the clock signal is within the first frequency range and to be inactive when the rate is outside of the first frequency range. Further, the second tuned circuit and the driver circuit may be collectively tuned according to a second frequency range that is different from the first frequency range. The second tuned circuit may be configured to be active when the rate is within the second frequency range and to be inactive when the rate is outside of the second frequency range.

Abstract: A method is disclosed. The method may include detecting whether a first electronic device is in an inserted state in a second electronic device. The method may include switching the first electronic device to an “on” state in response to detecting that the first electronic device is in the inserted state in the second electronic device. In particular, the first electronic device may function as a master device and the second device may function as a slave device in response to the first electronic device switching to the “on” state. An electronic device and a program product are also disclosed.

Abstract: An information processing apparatus having a function of entering and returning from a hibernation state and communicable with a server apparatus performing device certification includes a storage unit configured to, in a case where a software module is activated, store a hash value of the activated software module in a volatile memory, a request unit configured to request device certification based on a hash value stored in the volatile memory from the server apparatus, and an excluding unit configured to, in a case where the device certification is requested after returning from the hibernation state, exclude a software module activated before entering the hibernation state from a target of the device certification.

Abstract: A loading order according to which function modules are to be loaded from a storage unit is determined based on a predicted use situation of a user. The function modules are loaded according to the loading order thus determined. Subsequently, the function modules thus loaded are started up according to a start-up instruction. With such an arrangement, by determining the loading order based on a prediction of the user's desired function, such an arrangement enables a reduction in the length of a loading time that bothers the user.

Abstract: A voltage regulation (VR) module of an Information Handling System (IHS) operates a switching direct current to direct current (DC-DC) voltage regulation (VR) power circuit in a constant current mode at a constant current level. The VR module approximates the capacitance value of the output capacitive load at the output terminal of the switching DC-DC VR power circuit based upon a time interval for output voltage to reach a threshold. The VR module then operates the switching DC-DC power circuit in constant output voltage mode using one group of VR operating settings to optimize performance for the capacitance value of the output capacitive load.