Abstract: A power-on-reset circuit for delivering a power-on-reset pulse when a supply voltage ramps up from zero to a predetermined voltage includes a pull-down circuit portion for connecting an output node of the power-on-reset circuit to ground when the supply voltage reaches a predetermined upper threshold voltage and a pull-up circuit portion for connecting the output node to the supply voltage when the supply voltage reaches a predetermined upper threshold voltage. The pull-up circuit portion includes a transistor whose gate is polarized by a reference voltage taken at the terminals of a precision resistance traversed by a current delivered by a current generator, where the current is preferably a band-gap current proportional to the temperature of the circuit. The power-on-reset circuit is particularly suitable for microprocessors.
Abstract: A gating circuit for largely glitch-free gating of analog signal values obtained in a periodic sequence, capacitively buffer-stored, digitized by means of an A/D converter and subsequently erased before a next signal value is obtained in the capacitive buffer store. A first operational transconductance amplifier (OTA) capable of being activated by a gating pulse has a non-inverting input connected to the reference-earth point of a capacitive store and an output connected to the charging terminal of the capacitive store. Its inverting input is connected through an impedance converter and a resistor, which limits the discharge current, to the charging terminal of the capacitive store. A second OTA serves as a signal driver whose gain is predetermined by the ratio of the value of a resistor connected in parallel with the capacitive store to that of a series resistor that determines the potential at the inverting input of the second OTA.
Abstract: A phase detector circuit receives both a reference clock signal and a sense clock signal and produces a synchronization signal if the sense and reference clock signals are in phase within a specified tolerance. A lead/lag signal is provided to a skew control circuit and accompanying delay circuits to increase or decrease the amount of delay on the reference clock signal and the sense clock signal if the two signals are not in phase within the specified tolerance. The sense clock signal is a feedback signal returned from logic circuitry, which originally receives the reference clock signal, which may be supplied by a master clock signal within a processor.
September 11, 1995
Date of Patent:
June 29, 1999
International Business Machines Corp.
Humberto Felipe Casal, Hehching Harry Li, Trong Duc Nguyen
Abstract: A high voltage generator circuit comprises a boosting circuit, limiter circuit, and a bypass circuit. When a supply voltage is inputted into the boosting circuit, a high voltage is generated and supplied to the limiter circuit. When the high voltage generated by the boosting circuit exceeds a limit voltage of the limiter circuit, the limiter circuit operates and the output voltage of the boosting circuit is thus maintained at a constant value. When the output voltage exceeds the limit voltage of the limiter circuit and an output current of the boosting circuit exceeds a reference value, a portion of the output current of the boosting circuit equivalent to a difference between the output current and a predetermined value is bypassed and discharged by the bypass circuit stated above.
Abstract: A self-resetting logic stage provides for a relatively faster propagation of pulse signals and for relatively less power consumption. For a self-resetting logic stage in a digital logic path of successive logic stages, a forward path creates the forward edge for an output pulse signal and a reset path creates a reset or trailing edge for the output pulse signal. The propagation delay for the reset path may be increased for successive stages in the logic path to minimize or avoid overlap current. As the increased propagation delay increases the width of a pulse signal as the pulse signal propagates from stage to stage, logic stages in the logic path may be configured to reduce the width of the pulse signal, for example when the pulse signal approaches a width that may limit the cycle time for the logic path. Logic stages in the logic path may also be configured to provide for relatively quicker reset recovery to minimize any increase in cycle time.
January 27, 1997
Date of Patent:
January 26, 1999
Cypress Semiconductor Corporation
Raymond E. Bloker, Ashish Pancholy, Gary A. Gibbs
Abstract: The bias control means determines the operating mode only when the trigger input comes into a valid state or the inverted output signal is low level, and determines the power saving mode in other cases. During the power saving mode, the comparator does not operate since a bias current is not supplied, therefore, the pulse generator of the present invention can attain a low power consumption. Also, the pulse generator of the present invention can generate an output signal having a desired width regardless of the width of the trigger input.
Abstract: A substrate voltage generating circuitry for a dynamic random access memory (DRAM) generates the substrate voltage using an intermittently enabled charge pump. The value to which the substrate voltage is regulated is adjusted responsive to the static refresh and dynamic refresh characteristics of the memory cells. The adjustment is made in the portion of the substrate voltage generating circuit used for sensing the substrate potential, using fusible links that can be interrupted or cut with a laser beam. Novel circuitry for sensing the substrate potential, which does not load the substrate so as to dissipate charge placed thereon by the charge pump, is used in preferred substrate voltage generating circuitry.
Abstract: An additional MOS transistor receiving at its control electrode a signal complementary to that applied to control electrodes of MOS transistors is provided between a power supply node and a control electrode line formed by resistors having a significant resistance and interconnecting respective control electrodes of MOS transistors which are connected in parallel and each of which is connected between output signal line and power supply node. When MOS transistors are rendered non-conductive, the additional MOS transistor is rendered conductive. As a result, internal nodes are driven by an inverter and the additional MOS transistor to a power supply voltage, thereby turning off MOS transistors at the same timing. Consequently, through current in a semiconductor output circuit can be suppressed and an output signal has no ringing.
Abstract: A negative voltage drive circuit according to the present invention comprises a switching means coupled between an input terminal and an output terminal; a cross latch pumping means for controlling the switching means in response to first and second clock signals and for maintaining the lower output voltage than that of said charge pump; and a capacitor which starts pumping operation according to the first clock signal when the output terminal is isolated to the input terminal.
Abstract: A method for compensating for position and component induced variations in the acceleration and deceleration capabilities of a voice coil actuator in a disc drive, comprising the steps of dividing the discs radially into a plurality of zones, testing the acceleration and deceleration capability of the disc drive in each zone by performing specially controlled seeks in both inward and outward directions in each zone, comparing the result of these specially controlled seeks with a calculated nominal or desired result, and calculating a compensation factor for each zone which is applied by the servo system to all subsequent seek and track following operations.
March 21, 1994
Date of Patent:
November 10, 1998
Seagate Technology, Inc.
Otis L. Funches, Randall D. Hampshire, Vladimir Kovner
Abstract: A low power regenerative feedback device and method automatically increases bias current during positive large-signal slewing, enabling output to change faster. When the device is not in a positive slew, bias currents are unchanged, providing a low standby current. Since regenerative feedback is internal and automatic to the device, current is increased only for the device driving an active column of an LCD panel. Thus, the present invention is power efficient. In addition, the AC response of the device is preserved because the device utilizes a regenerative feedback circuit that does not add appreciable excess phase shift. The device achieves an output that switches readily from positive supply to negative supply.
Abstract: The present invention provides an input buffer circuit for reducing false transitions within a circuit. The input buffer circuit includes an input pad for receiving an input voltage, an input buffer having an input and a circuit for modifying a voltage entering the input buffer to track changes in a power supply voltage relative to a voltage at the input pad. The circuit is connected in series between the input pad and the input the input buffer.
Abstract: A voltage regulator (10) is provided. A first bipolar transistor (24) has an emitter connected to a first node (NODE 6) and a base connected to a second node (NODE 5). A second bipolar transistor (30) is scaled N:1 with respect to the first bipolar transistor (24), N greater than one. The second bipolar transistor (30) has an emitter, a base, and a lateral collector. The base is connected to the second node (NODE 5). A first resistor (20) is connected between the first node (NODE 6) and an output node (NODE 2). A second resistor (32) is connected between the first node (NODE 6) and the emitter of the second bipolar transistor (30), and a third resistor (22) is connected between the first node (NODE 6) and a ground node (GND). A current sensing amplifier (12, 14, 34, 38 and 40) has a first input node (NODE 7) connected to the lateral collector of the first bipolar transistor (24) and a second input node (NODE 8) connected to the lateral collector of the second bipolar transistor (30).
Abstract: A dc-stabilized power circuit which has a PNP-type output transistor that is connected between input and output terminals, a base-driving circuit for controlling the driving current of the base of the output transistor in response to the difference between a voltage obtained by voltage-dividing the output voltage from the output terminal and a reference voltage that has been preliminarily determined, and a driving-current suppressing circuit for detecting a voltage between the input and output terminals and for suppressing a driving current released by the driving-current supplying means based upon the result of the detection. The greater the input-output voltage, the further the driving-current suppressing circuit suppresses the driving current from the base-driving circuit to the output transistor, thereby suppressing the output current.
Abstract: A signal transmission circuit which enables the distance of signal transmission as measured by the length of the wiring electrically connecting a driver circuit and a receiver circuit of the signal transmission circuit to be increased, while the signal delay and power consumption are reduced. The signal transmission circuit includes the driver circuit, the receiver circuit, an equalizer circuit that flattens the output of the driver circuit, and an intermediate amplifier circuit. The intermediate amplifier circuit is connected to input/output shared terminals in the wiring that connects the driver circuit and the receiver circuit. With the aid of the positive feedback of the intermediate amplifier circuit, a differential signal output from the driver circuit is amplified and then transmitted to the receiver circuit.
Abstract: A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to the product of first and second differential input voltages has first and second two-quadrant multipliers each having a differential output. The combined differential output current includes a plurality of differential output currents. First and second two-quadrant multipliers included in the MOS four-quadrant multiplier each have first and second pairs of transistors including sources connected in common to each other. A third pair of transistors is connected in cascode to the first pair of transistors as a load on the first pair of transistors. In each of the two-quadrant multipliers, the second pair of transistors has drains which are not connected in common to drains of the third pair of transistors. The second pair of transistors has gates respectively connected to drains of said first pair of transistors and sources of said third pair of transistors.
Abstract: A differential voltage reference circuit implemented in CMOS provides a continuous differential voltage having good substrate and supply noise-rejection and low power consumption. The differential voltage reference is operable under a low voltage power supply in the range of 1-3 volts and does not require a large silicon die area. The differential voltage reference includes two parasitic bipolar transistors and a single differential summing amplifier. PTAT and CTAT differential signals are summed at the amplifier summing junctions to provide a temperature-independent differential reference voltage. The differential amplifier maintains a common-mode level of the output at a constant level with respect to a bias voltage at the bases of the two bipolar transistors.
Abstract: A power-on-reset (P.O.R.) circuit produces a power-on-reset (P.O.R.) signal whose an amplitude tracks the voltage on a supply node until it exceeds a certain threshold. The circuit has a first monitoring and comparing circuit portion including at least a nonvolatile memory element having a control gate coupled to the supply node, a first current terminal coupled to a ground node, and a second current terminal coupled to a first node which is capacitively coupled to the supply node. The circuit further includes a second circuit portion that includes an intrinsically unbalanced bistable circuit, having a node that intrinsically is in a high state at power-on coupled to the first node that is intrinsically in a low state at power-on coupled to the input of an output buffer.
January 30, 1997
Date of Patent:
October 13, 1998
SGS-Thomson Microelectronics S.r.l.
Luigi Pascucci, Paolo Rolandi, Marco Fontana, Antonio Barcella
Abstract: A variable delay circuit including an input terminal to which a signal to be delayed is input, a delay gate connected to the input terminal, a logical gate to which an input to the delay gate and an output from the delay gate are input and which forms a delayed signal, and an output terminal outputting the delayed signal formed by the logical gate. A control signal for controlling the delay gate is input to the delay gate.
Abstract: In a charge pump circuit having a plurality of transistors connected in a diode configuration, the threshold voltage of the transistors are prevented from being increased due to a back-bias effect by having the threshold biases of the transistors adjusted. The circuit, therefore, ensures a desired voltage boosting ability.