Abstract: A totem pole driver with cross conductive protection and default low impedance state output employs a totem pole output formed by top and bottom output transistors. A first circuit path switches the bottom output transistor on or off in response to a switching signal. A second circuit path, slower than the first circuit path, switches the top output transistor on in response to the switching signal after the bottom output transistor is switched off. A third circuit path switches the top output transistor off in response to a sync signal known to lead the switching signal. An emergency voltage supply is made available to hold the bottom output transistor on and the top output transistor off if the regulated circuit voltage is lost.

Abstract: A means and method for testing high speed phase locked loops (13) in an integrated circuit (12) at a test frequency lower than the operation speed of the phase locked loop (13). A test circuit portion (10) repeatedly tests for a zero level (42) of a recover clock signal (34) from the phase locked loop (13) and a latching flip flop (26) is set to provide a lock indication output (30) as long as repeated samples, taken at a test time (38) continue to indicate a zero level (42) of the recover clock signal (34). The test time (38) is the leading edge (40) of a reference clock signal (36) provided from an external source at a reference clock input (28) to the integrated circuit (12).

Abstract: An object of the invention is to provide a variable delay circuit having a desired optional resolution.A variable delay section 24 is provided with paths A and B which carry signals input to an input terminal 21 to an output terminal 22, and a selection section for switching the paths A and B in accordance with a select signal. Ring oscillators 25 and 29 have oscillation periods which are x times and y times the delay time of the respective paths A and B. Phase comparison circuits 27 and 31 respectively compare, the phase of a first clock signal and the output from the ring oscillator 25, and the phase of a second clock signal and the output from the ring oscillator 29. Delay time control circuits 28 and 32 then respectively control the oscillation periods of the ring oscillators 25 and 29 so as to be equal to the respective periods of the first clock signal and the second clock signal, based on the phase comparison results, and control the delay times of the paths A and B.

Abstract: A direct current sum bandgap voltage comparator for detecting voltage changes in a power supply. The direct current sum bandgap voltage comparator includes a summing node, current sources connected to the summing node and the power supply, and an indicator circuit connected to the summing node. Each current source supplies a current to the summing node wherein the summing node voltage level is responsive to the currents supplied. The indicator circuit is responsive to changes in the summing node voltage level and generates at an output a logical signal at one state when the summing node voltage level is greater than a predetermined value and generates the logical signal at the output at another state when the summing node voltage level is less than the predetermined value, the predetermined value corresponding to a preselected power supply voltage.

Abstract: A device for copying a voltage (Ve) comprises a pair of series-connected MOS transistors, their sources forming a common point. The voltage (Ve) to be copied is applied between the gate of the first MOS transistor of the pair and a reference. Means are provided to inject a flux of electrons at a common point. A storage capacitor has a first terminal connected to the drain of the second MOS transistor and a second terminal designed to be biased. Means dictate a potential at the drain of the second MOS transistor and then let it vary so that the flux of electrons is stored in the storage capacitor while at the same time decreasing in the second MOS transistor to the benefit of the first one. The copied voltage Vs is available, after stabilization, between the first terminal of the storage capacitor and the reference. Application in particular to circuits for the reading of charges generated in a photosensitive matrix or photosensitive linear array.

Abstract: A multi-purpose current source which provides both a PTAT and a constant current source and which requires only one precision external or laser trimmed resistance. The PTAT constant current circuit includes a differential amplifier having one input coupled to a V.sub.PTAT reference voltage and the other input coupled to a V.sub.bg scaling circuit. The tail current for the differential amplifier is held constant at the current level of an associated constant current source based upon V.sub.bg. Therefore, the amount of current output from the PTAT current source will be dependent upon the current of the constant current source, rather than upon a resistance value. By setting the scaling circuit appropriately, the current that flows through the output leg of the differential amplifier in the PTAT current source when the ambient temperature is equal to 25.degree. C. will be equal to one half the tail current through the differential amplifier, and thus one half the current output from the constant current source.

Abstract: A MOS four-quadrant multiplier for outputting a combined differential output current corresponding to the product of first and second differential input voltages has first and second two-quadrant multipliers each having a differential output. Each of the first and second two-quadrant multipliers has first and second pairs of transistors having sources connected in common to each other, and a third pair of transistors connected in cascode to the first pair of transistors as a load on the first pair of transistors. In each of the two-quadrant multipliers, the second pair of transistors has drains not cross-coupled to drains of the third pair of transistors, the second pair of transistors has gates connected to drains of the first pair of transistors, respectively, and the third pair of transistors has gates connected in common to each other at a node. The differential output current of each two-quadrant multiplier contains at least a drain current of the second pair of transistors.

Abstract: A one-diode circuit for negated implication (.about..fwdarw.) is derived from a 12-transistor Lukasiewicz implication circuit (.fwdarw.). The derivation also yields an adjustable three-transistor implication circuit with maximum error less than 1% of full scale. Two Lukasiewicz logic arrays (.English Pound.LAs) are proposed that use area-efficient implementations of the one-diode and three-transistor implication circuits. The very dense diode-tower .English Pound.LA contains 36,000 implications in an area that previously held 92 implications; the three-transistor .English Pound.LA contains 1,990 implications. Both .English Pound.LAs double the number of inputs per pin on the IC package. Very dense .English Pound.LAs make .English Pound.LA-based fuzzy controllers and neural networks practical. As an example, an .English Pound.LA retina that detects edges in 15 nanoseconds is described.

Abstract: Disclosed are method and apparatus for producing electric waveform driver signals for exciting acoustic emitters such as foghorns, wherein the frequency and amplitude of the signals are readily variable to match the input requirements of the respective drivers of the acoustic devices. In disclosed embodiments of a signal generator according to the present invention a coupling circuit outputs the driver signal through an array of field-effect transistors.

Abstract: A semiconductor device includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse width at a rise or fall timing of a first clock signal, a cycle time measuring circuit that measures a cycle time of the first clock signal from the one-shot pulse output from the one-shot pulse generating circuit, an internal clock generating circuit that generates a second clock signal based on the cycle time measured by the cycle time measuring circuit and the one-shot pulse output from the one-shot pulse generating circuit. The second clock signal has a cycle time identical to the first clock signal and has rise or fall timing which is advanced by a specific time than that of the first clock signal, and the specific time is obtained by subtracting the cycle time of the first clock signal from a predetermined time, and a data output circuit that outputs data after a predetermined delay time from the rise or fall timing of the second clock signal.

Abstract: According to the present invention, there is provided an integrated circuit useful in an electronic encoding device having a voltage source, a user interface and a transmitter. In one embodiment the integrated circuit includes a wake-up circuit which generates a signal responsive to an input received from the user interface; power switching logic which provides power from the voltage source to a non-regulated power bus and a voltage regulating circuit, the power switching logic being responsive to the signal from the wake-up circuit; a regulated power bus in communication with the voltage regulating circuit; non-volatile memory in communication with the regulated power bus; encoder logic in communication with the regulated power bus, the encoder logic having output logic which provides a signal to the transmitter.

Abstract: A latch comprises first and second NFETs and a first inverter. Data is applied without inversion to the gate of the first NFET and via the first inverter to the gate of the second NFET. A third NFET has a drain connected to the sources of the first and second NFETs. A clock is applied to the gate of the third NFET. Thus, there is only one NFET subject to the constant switching the clock, and therefore the constant power dissipation caused by the clock. To latch the data from the first and second NFETS, first and second inverters are connected in paralle with each other such that the output of each inverter is connected to the input of the other inverter. The input of one of the inverters is connected to the drain of the first NFET and the input of the other inverter is connected to the drain of the second NFET. A second stage of latching is also disclosed.

Abstract: A semiconductor integrated circuit device includes a reference voltage generating circuit outputting a reference voltage from a step-up voltage, a step-up circuit stepping up the reference voltage within a range lower than an external power supply voltage and thus outputting the above step-up voltage, a step-down circuit stepping down the external power supply voltage and thus outputting a step-down voltage equal to the reference voltage, and an internal circuit receiving, as a power supply voltage thereof, the step-down voltage.

Abstract: The present invention is directed toward a circuit for receiving an input current and for producing an output voltage proportional to the input current. The circuit includes a first transistor which receives the input current, and a second transistor connected to the first transistor, wherein the first and second transistors comprise a current mirror topology. A third transistor is connected in series with the first transistor, and an operational amplifier has an output which is connected to the base of the third transistor. The third transistor has a collector coupled to a base junction of the current mirror. The operational amplifier has a positive input terminal coupled to a collector of the second transistor through a first resistor, and a negative input terminal coupled to an emitter of the third transistor through a second resistor, the first and second resistors having substantially similar impedance values.

Abstract: The present invention relates to a filter circuit which is suitable for use in an integrated circuit formed of transistors or field effect transistors, and controls the frequency band of the amplifying circuit used for the signal receiver, for example, within an optical communications system. The filter circuit includes a first transistor (T1) having a base or gate grounded with high-frequency component via a first resistor (R1); and a second resistor (R2) and a capacitor (C1) each having one end connected to the emitter or source of the first transistor (T1) and the other terminal grounded with high-frequency component. The filter circuit acts as a circuit in which the first transistor (T1) inputs the current (Iin) at a juncture at which the second resistor (R2) and the capacitor (C1) are connected therewith and outputs its collector or drain current (Iout).

Abstract: A method and an apparatus for generating an output voltage for an integrated circuit having multiple power supplies. A comparator circuit is coupled to receive power supply lines from the power bus of an integrated circuit. The power supply lines received from the power bus have different voltages which may vary depending on the particular application. The comparator compares the voltage potentials present on the power supply lines and determines which power supply line carries a voltage having the highest potential. The comparator then generates a corresponding select signal wherein the value of the select signal indicates which particular power supply line has the highest voltage potential. A multiplexor is coupled to receive the select signal as well as the power supply lines from the power bus.

Abstract: A substrate bias voltage controlling circuit controls the generation of different substrate bias voltages according to specific modes. A first sensing signal generator is controlled by the substrate bias voltage and generates a first sensing signal when the level of the substrate bias voltage is higher than a predetermined first potential level. A second sensing signal generator is controlled by the substrate bias voltage and a specific mode signal and generates a second sensing signal when the level of the substrate bias voltage is higher than a predetermined second potential level and when the mode signal is enabled.

Abstract: A level-shifting circuit (LS.sub.A) including a series arrangement of a load resistor (R.sub.A), a main current path of an input transistor and a bipolar series transistor (T3.sub.A) arranged as a current source and having a parasitic transistor with a small current gain factor, which is obtained, for example, by wholly surrounding the comparatively weakly doped collector region with a comparatively heavily doped material of the same conductivity type as the collector region. When the input transistor (T1.sub.A) is not conductive a large amount of charge accumulates in the series transistor (T3.sub.A), which is then in saturation. When the input transistor (T1.sub.A) is turned on the accumulated charge causes an overshoot in the current (I.sub.A) through the level-shifter which overshoot compensates for the slow response as a result of the parasitic capacitance (PC.sub.A) at the node (N.sub.A).

Abstract: A circuit suitable for use in a regulated bi-directional output power supply requiring controlled transitions between states, such as in a Battery Polarity Switch is provided to utilize many of the same circuit components in regulating both opposing polarities of the output signal. An exemplary circuit achieves use of a single error amplifier and pulse width modulator circuit to obtain both positive and negative regulation of the battery polarity switch output, along with controlled transition between the two states. In a specific embodiment a logic inverter allows the single pulse width modulator to control in both directions. A ramped reference fed to the error amplifier allows the same amplifier to control the transitions.

Abstract: A power control circuit of a monitor capable of being applied to all kinds of monitors is constructed to supply a control signal in accordance with the state of the monitor among On, Stand-by, Suspend and Off states by considering the input of vertical and horizontal sync signals after checking the current input state of the horizontal and vertical sync signals of the monitor, thereby facilitating the embodiment of the circuit that provides the control signal according to the current power supply state of the monitor by an ASIC.