Abstract: The gate of an NMOS transistor receives a reference potential, and the source is connected to an output node. A load element is provided between the drain of this transistor and a power supply. First and second inverter circuits sequentially invert a drain potential of the NMOS transistor and transfer it to the gate of a PMOS transistor. The source of the PMOS transistor is connected to a power supply, and the drain is connected to the output node. When the potential of the output node becomes lower than a reference potential, the PMOS transistor is activated until the outputs from the inverter circuits are inverted, thereby charging the output node with a large current.

Abstract: An integrated circuit voltage converter containing a capacitive charge pump performing DC to DC conversion is disclosed which detects, either automatically or by an external signal, the onset of a low power consumption situation and switches to a low power consumption mode. In one embodiment, the low power consumption mode is accomplished by reducing the operating frequency of the charge pump. In another embodiment, the switching transistors used to switch the capacitors in the charge pump during a low power consumption mode are smaller than those transistors used to switch the capacitors during its normal operating mode. In another embodiment, the DC to DC converter switches back and forth between a high frequency (burst) mode and a low frequency (low power) mode at intervals. In another embodiment, a combination of the power reduction techniques is used. Various techniques for detecting when a low power consumption mode is appropriate are also described.

Abstract: Switching regulator circuits and methods are provided in which the output circuit is adaptable to maintain high efficiency over various load current levels. The regulator circuits generate one or more control signals in response to the load current and selectively route a switch driver control signal to one or more switches in the output circuit. The switches differ in their size, such that the most efficient switch can be used at a particular load current level. At low load current levels, the driver control signal is routed to output circuitry with smaller switch devices, which incur smaller driver current losses for a given frequency of operation, thereby increasing the regulator efficiency. At high load current levels, the driver control signal is routed to large switch devices, which incur greater driver current losses for a given frequency of operation, but which have a lower impedance.

Abstract: A system for synthesizing a waveform includes waveform synthesis circuitry that generates digital data for each of a set of waveform pulses having preselected slopes at zero-crossing. A sequencer tracks the history of information contained in a data signal and selects a sequence of the waveform pulses in response to the history such that the sequence conveys the history of information while minimizing mismatches between the slopes of adjacent waveform pulses in the sequence.

Abstract: A phase current reconstruction circuit (10) senses and reconstructs a phase current in a phase bridges (12A). An amplifier (32) in a phase current reconstruction element (22) amplifies a voltage signal across a sensing resistor (18). The amplified voltage signal is transmitted to a sample and hold circuit (34), which reconstructs the phase current in the phase bridge (12A). An over-current comparator (36) compares the amplified voltage signal with a predetermined reference voltage to detect an over-current in the phase bridge(12A). If the over-current in the phase bridge (12A) is detected, an over-current latch (38) interrupts the pulse width modulation signal from a microcontroller (26) to a power switch (16A) in the phase bridge (12A), thereby switching off and protecting the power switch (16A) from damage that may be caused by the over-current.

Abstract: A variable load current supply unit supplies a current to be consumed by a constant voltage output unit to a power source terminal thereof, and supplies a current to be consumed by a load circuit thereto through a reference voltage output terminal. The constant voltage output unit maintains a potential of the power source terminal thereof, i.e., a potential of the reference voltage output terminal, at a fixed potential. A base potential control unit negatively feeds back changes in the potential on the reference voltage output terminal to a base of an emitter follower transistor in the variable load current supply unit. In this way, when the current consumed by the load current is reduced and the potential on the reference voltage output terminal thereby slightly increases the current supplied by the variable load current supply unit decreases.

Abstract: A current comparator arrangement has first and second inputs (100, 103), an output (105), and cross-coupled transistors (MP1, MP2) which form a latching circuit. The arrangement also includes current stores (MP3, MP4), the input currents to be compared being fed to the current stores in a selected forward differential order for storage therein during a first portion of a clock period in which the cross-coupled latching circuit is reset. During a second portion of the clock period the input current connections are reversed, thereby reversing their differential order, and the reverse order currents are supplied together with the stored forward order currents to the latching circuit. This cancels common mode and offset currents so that they do not affect the comparison of the input currents.

Abstract: A voltage regulator for electrically programmable, non-volatile memory devices has an output terminal connected to a power supply line for programming the state of at least one memory element through at least one selection circuit. At least first and second resistive elements are connected between first and second terminals of a voltage supply. At least a first circuit is matched to the at least one selection circuit, and the first circuit is coupled serially with the resistive elements between the two terminals of the voltage supply. At least one control current generator is connected between one of the first and second voltage supply terminals and a node linking to one of the resistive elements, and the current of the controlled current generator is controlled to be a function of current through the at least one selection circuit. An operational amplifier has an inverting input and a non-inverting input, and the non-inverting input is connected to a node linking to at least one of the resistive elements.

Abstract: A boost circuit effects increasing current flow through an inductor and a switch when the switch is closed, and then, when the switch is open, directs the inductor current through a diode to charge a storage capacitor at the output. A logic circuit operates the switch. The switch is controlled on by sensing low current flow in the capacitor and off by sensing high current flow in the switch, so that inductor current is continuous.

Abstract: An NMOS transistor (2) has a source electrode, a drain electrode and a gate electrode which are connected to a power source (VSS), an output terminal of a stepdown circuit (27), and a node (N2) between load elements (11, 12) respectively. The transistor size of the NMOS transistor (2) is so set that its drain current exerts no influence on fluctuation of an output voltage (VDD2) when an output voltage control operation by a differential amplification circuit (29) and the stepdown circuit (27) is functional to enable suppression of fluctuation of the output voltage (VDD2), while the output voltage (VDD2) is stepped down on the basis of the current quantity of the drain current of the NMOS transistor (2) when the output voltage control operation is unfunctional to disable suppression of fluctuation of the output voltage (VDD2). Thus, obtained is a voltage generation circuit which can reliably suppress fluctuation of the output voltage regardless of the frequency of fluctuation in source voltage.

Abstract: A semiconductor integrated circuit comprises a NAND gate which constitutes a previous stage circuit, a reset circuit, a charging circuit, and a capacitor for generating a boost potential. A signal of a node A expressing data and a signal of a node B expressing permission of outputting data are not only input to the NAND gate, but also to the reset circuit, and the output of the reset circuit is not only input to the charging circuit but also to the NAND gate; therefore, the previous stage circuit and the reset circuit are interlinked with the output signals. In the result, even in a case where noise is generated in the node A, it is possible to obtain a sufficient boost potential generated in the capacitor.

Abstract: A substrate clamp for non-isolated integrated circuits is disclosed. The substrate clamp comprises a circuit that controls the voltage on a substrate so that the substrate is connected to a specific node if the parasitic PN diodes at all the circuit nodes are not forward biased. If a specific node is then forced with an applied voltage to forward bias, the substrate is disconnected from its original node and maintains itself at a forward biased diode voltage drop away from the powered node. Various embodiments are disclosed. In one embodiment of the invention, a set of bipolar transistors which utilize the substrate as a common base, is implemented. The emitters of these transistors are connected to a set of nodes which may be driven to voltages outside the range between that provided by the power supply and ground, or any other pair of applied voltages. The collectors of these bipolar transistors are connected together.

Abstract: A substrate bias generator for an integrated circuit has a charge pump driven by an oscillator. The oscillator is enabled and disabled to save power and control the voltage-level itself for the substrate bias. An enabling circuit senses the substrate voltage and enables the oscillator when the substrate voltage rises above a bias set by a programmable reference voltage. The enabling circuit which senses the voltage on the substrate draws no active current from the substrate. The sensing circuit includes a transistor with only its bulk terminal connected to the substrate; the source, gate, and drain of this sensing transistor are not connected to the substrate. A differential comparator compares the output of the sensing transistor to the programmable reference voltage and enables the oscillator when the sensing transistor output is lower than the reference voltage.

Abstract: A high side monolithic switching circuit integrated into a silicon chip is described in which the charge pump is connected to the ground terminal by a constant current circuit and floats relative to the ground terminal to reduce noise generation. The charge pump is connected to a V.sub.CC terminal by an auxiliary power MOSFET having its gate connected to the charge pump output circuit. The conventional charge pump diodes are implemented as MOSFET devices which can be easily integrated into the common monolithic chip. A clamping circuit across the charge pump permits the use of a low voltage, small area capacitor for a high voltage device.

Abstract: In a circuit provided in a single integrated circuit unit for use in a signal delay device, there is provided with a device in which an input signal is delayed and a plurality of delay signals, each having a different delay period from the input signal, are outputted, and a detector in which a delay signal having a specific relation with the input signal among the plurality of delay signals is detected.

Abstract: A sensor apparatus is capable of removing RF noise. The sensor apparatus is comprised of a first power supply line connected to a power supply terminal; a second power supply line separately branched from the first power supply line and connected thereto; an output line; and a sensor circuit unit connected to the first power supply line so as to receive power therefrom, and for detecting a condition of an article under measurement to output a detection signal to the output line. In this sensor apparatus, the sensor circuit unit includes an operational amplifier operated by accepting the power supplied from the second power supply line, which performs the detection operation; a first filter circuit is connected to the first power supply line defined from a branch point between the first power supply line and the second power supply line to the first power supply line; a second filter circuit is connected to the second power supply line; and a third filter circuit is connected to the output line.

Abstract: A differential, interpolating, switched capacitor filter and method of operation in which non-interpolating stages of the filter are clocked at a first frequency and a subsequent interpolating stage of the filter is operated at double the first frequency to achieve improved smoothing of the output wave form. The switched capacitors in the interpolating stage which feed forward a differential input from a prior stage to an input to the interpolating stage, and which feed a differential output from the interpolating stage back to an input thereto are paired and switches are provided for the added capacitors so that all of these capacitors are switched. Capacitors which are directly coupled to feed forward a differential input from a prior stage to the interpolating stage are also paired, but only the added capacitor is switched.

Abstract: A graphics engine is disclosed which can be used in a color desktop publishing system. The graphics engine accepts 32-bit RGBM data and performs pixel level calculations under computer control to output processed 32-bit RGBM data The engine comprises a render processor interface, a run controller including a ramp generator, and a control unit. Interpolators are provided for each color (RGB) and cascaded with corresponding compositors. A transparency interpolator and matte combiner alter the matte plane of the video image. The engine can output data suitable for rendering by a color laser printer for a full size A3 page at 400 dots per inch.

Abstract: A potential detecting circuit comprises a MOSFET, a constant current circuit, a reference potential generating circuit and a comparing circuit. A power supply potential is applied to a drain of the MOSFET and a subject potential to be detected is applied to the gate of the MOSFET. The constant current circuit is connected to a source of the MOSFET. The comparing circuit compares a reference potential output from the reference potential generating circuit with a source potential of the MOSFET. A detection output is obtained on the basis of the comparison result. The source potential of the MOSFET is increased in accordance with an increase of the subject potential. When the source potential coincides with the reference potential output from the reference potential generating circuit, the level of the source potential is detected as a detection level.

Abstract: An LSI device can provide a desired constant value of a step-down voltage even if there are variations due to the production processes and a stable characteristic of internal circuits is obtained. The LSI device such as a DRAM includes a first input terminal of the high-voltage-side external supply voltage, a constant current source and a second input terminal of the low-voltage-side supply voltage. Further, the device includes a circuit which makes a voltage between two terminals variable due to the disconnection of each fuse. A step-down circuit is formed by the constant current source and the load circuit and provides a step-down voltage V.sub.B for stepping down the external supply voltage V.sub.CC.