Abstract: A delay for short power interruptions by using a first comparator to compare the power supply voltage to a voltage reference. A second comparator has a first input coupled to the same voltage reference, and an output which generates the reset signal. A capacitor coupled to the second input of the second comparator determines when a reset signal is issued. The capacitor is normally charged by a current source. When the power supply falls below a set point indexed to the reference voltage, as indicated by the first comparator, a discharging circuit discharges the capacitor. The rate at which the capacitor is discharged and the threshold of the second comparator determines how long of a power interrupt is required to issue a reset signal. In the preferred embodiment, the discharging circuit is a latching current source. The current source is latched into the on position by the output of the comparator, and is reset when the comparator indicates that the voltage supply is returned to normal.

Abstract: In a bias voltage controlling apparatus, a bias voltage comparator circuit compares a bias voltage with a reference voltage. When the bias voltage is higher than the reference voltage, a bias voltage lowering circuit lowers the bias voltage. When the bias voltage is not higher than the reference voltage, a bias voltage lowering circuit raises the bias voltage.

Abstract: A fully integrated voltage-to-current converter consisting of a two-stage direct amplifier with an overall feedback network having an active differential current-to-voltage converter. The first stage of the two-stage direct amplifier is a voltage-to-voltage converter receiving an input voltage signal, and the second stage is a transconductance amplifier supplying an output current. In the overall feedback network, a voltage measure of the output current is applied to a differential amplifier which cancels out all DC components and amplifies only the AC components. The amplified AC components are fed back to the input. The feedforward gain of the two-stage direct amplifier and the feedback gain of the overall feedback network may be separately adjusted. The differential amplifier includes a local resistive feedback network such that the local gain of the differential amplifier is determined by resistor values and does not introduce any non-linear elements.

Abstract: A semiconductor circuit is so constructed that one of a plurality of different potentials is supplied to sources of FETs via a switching circuit, so as to vary the threshold voltage of the FETs in accordance with the operating state of the semiconductor circuit, thereby decreasing the waste of power.

Abstract: A controlled delay path inserts a selected delay into a clock distribution circuit to create a total clock delay that is equal to an integer number of clock cycles relative to a reference dock signal or which produces a selected phase relationship to the reference dock signal. The delay path correction of the invention is particularly useful in circuits having a wide range of possible system clock frequencies or having programmable routing of clock signals, and therefore a wide range of operating delays. A reference clock signal is directed to a range of selectable voltage controlled delay elements by a phase detector that receives the reference clock signal and a feedback signal, and that produces an error voltage which adjusts the voltage controlled delay elements to produce an output clock signal. Additional selectable delays may be included that create offset options and allow selection of a leading, lagging, or in-phase reference dock/output clock relationship.

Abstract: The invention relates to a system for transmitting binary signals over a signal line to a signal detecting device, in which a DC source is temporarily connectable to the signal line for generating binary signals. A discharge circuit is connected to the signal line. In order to keep the power loss very low in such a system, discharge circuit (7) contains a switchable current sink (8) connected to a signal line (3). Discharge circuit (7) also has a threshold value determination device (19) connected to signal line (3) in parallel with switchable current sink (8). Output (26) of threshold value determination device (19) is connected with a control input (17) of switchable current sink (8).

Abstract: An object is to provide a semiconductor device having an internal power supply circuit capable of supplying stable internal power supply voltage while not increasing layout area. A differential amplifying circuit in a voltage down converter controls potential level V.sub.OUT of the drain of transistor P14 such that it attains the reference potential V.sub.REF. If the potential V.sub.OUT increases, the gate potential of transistor N12 increases because of coupling function of a capacitance C2, and the transistor is rendered conductive. Thus the potential level V.sub.OUT is pulled down. By contrast, if the potential level V.sub.OUT lowers, transistor P12 is rendered conductive, and the potential level V.sub.OUT is pulled up.

Abstract: A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.

Abstract: An integrated detection circuit (10) linearly charges capacitors (14) and (16) over time in response to particular states of an input signal (12). Outputs from the integrated detection circuit (10) are generated by differential pairs (39) when the charge on either of the capacitors (14) or (16) is equal to or greater than a reference voltage input to the differential pairs (39).

Abstract: A circuit provides a restart signal to indicate a zero crossing of a continuous varying signal. A zero phase signal is generalized based on a zero crossing of the continuous varying signal. The continuous varying signal is sampled and held in accordance with the zero crossing. The continuous varying signal is converted to complementary signals, and these complementary signals are in turn converted to a signal appropriate for CMOS circuits.

Abstract: A method and apparatus for reducing contention in an integrated circuit during power-up. According to one aspect of the invention, an initialization circuit is included in an integrated circuit. In response to receiving Vcc, the initialization circuit generates a substitute clock signal and a substitute reset signal. The substitute clock signal and substitute reset signal are substituted for an off chip generated clock signal and an off chip generated reset signal during power-up until a predetermined condition is met. In response to receiving the substitute clock signal and the substitute reset signal, a plurality of circuits on said integrated circuit are initialized.

Abstract: A protected switch has a power semiconductor device (P) having first and second main electrodes (D and S) for coupling a load (L) between first (2) and second (3) voltage supply lines, a control electrode (G) coupled to a control voltage supply line (4) and a sense electrode (S1) for providing in operation of the power semiconductor device a sense current that flows between the first (d) and sense electrodes (S1) and is indicative of the current that flows between the first (D) and second (S) main electrodes. A control arrangement (S) has a sense resistance (R4) coupled to the sense electrode (S1) and across which a sense voltage is developed by the sense current (I.sub.3). A control semiconductor device (M3) has its main electrodes coupled between the control electrode (G) and the second (S) main electrode of the power semiconductor device (P).

Abstract: The gate terminal of a FET is supplied with a bias voltage from a gate biasing circuit and a fluctuation in voltage V.sub.CS applied to a constant-current circuit is detected by a voltage-fluctuation detector. A gate-bias controller controls the gate biasing circuit to lower the gate bias voltage in a case where the fluctuation in voltage V.sub.CS has changed in an increasing direction, and to raise the gate bias voltage in a case where the fluctuation in voltage V.sub.CS has changed in the decreasing direction. Further, there are provided a plurality of constant-current sources having respective FETs and biasing circuits for setting a prescribed power-supply voltage characteristic and a prescribed temperature characteristic. A constant-current circuit is constructed by parallel-connecting the FETs in the plurality of constant-current sources through the drains and sources thereof.

Abstract: A selector switch circuit comprises an input terminal to receive a positive voltage, an input terminal to receive a negative voltage, a command input terminal to receive a first command logic signal and an output terminal to provide an output voltage. The output is connected selectively to one of the input terminals, the first and second input terminals being connected to the output terminal by means of a first transistor and a second transistor and the circuit comprising control means for the production, as a function of the command signal, of the control voltages applied to the control gates of the transistors for the selective connection of the output terminal to one of the input terminals.

Abstract: To a current mirror circuit or a voltage regulator are coupled a primary winding of a transformer (T.sub.3 or T.sub.4) or a choke coil (L.sub.2 or L.sub.3). Transistors (Q.sub.1 or Q.sub.2) making up a current mirror circuit or the voltage regulator are alternatingly bypassed by a bypass circuit constituted of a capacitor (C.sub.2) and other elements. A DC magnetization which may be otherwise caused in a core or a yoke of the transformer (T.sub.3) or the choke coil (L.sub.2) is canceled by allowing direct currents to flow in opposite directions to each other through the primary winding of the transformer (T.sub.4) or through the choke coil (L.sub.2). Alternatively, the DC magnetization which may be otherwise caused in the core or the yoke of the transformer (T.sub.4) or the choke coil (L.sub.3) is significantly suppressed by restricting the direct currents flowing through the primary winding of the transformer (T.sub.4) or the choke coil (L.sub.3).

Abstract: A voltage reference for a CMOS memory cell having PMOS and NMOS transistors with a common floating gate. The reference provides a more stable voltage than voltage supplied from the Vcc pin of a chip. In one embodiment, the reference includes PMOS and NMOS transistors having a common gate and common drains all connected together. A weak current source supplies current to the source of the PMOS transistor of the reference so that voltage at the source of the PMOS transistor of the reference equals the magnitude of the sum of threshold voltages (Vtn+Vtp) of the NMOS and PMOS transistors of the reference. The voltage at the source of the PMOS transistor of the reference is provided as a reference to the source of the PMOS transistor of the CMOS memory cell. The voltage at the drains of the PMOS and NMOS transistors of the reference are provided to a control gate of the CMOS memory cell.

Abstract: A timing signal generator adjustably times successive pulses of an output timing signal. The generator receives input data before each output pulse and controls the timing of that output pulse in accordance with the input data. The generator includes a circuit providing a set of 2N phase signals frequency locked to a reference clock signal but evenly distributed in phase. First and second selectors each sample the data once during each cycle of the clock signal. The sampled data tells the first selector whether it is to produce a first output signal during the next clock signal cycle and, if so, which of the first N phase signals the first selector is to select for controlling timing of edges of the first output signal. The sampled data also tells the second selector whether it is to produce a second output signal during a next clock signal cycle and, if so, which of the second N phase signals the second selector is to select for controlling the second output signal.

Abstract: A boost subject circuit block selector supplies a supply voltage to a corresponding boost voltage transmission line when a block selecting signal is at non-selecting level, while supplying a boost voltage from a boost voltage generator when the block selecting signal is at a selecting level. The boost subject circuit block selector includes a transistor, which is turned on in response to the transition of the block selecting signal to selecting level so as to supply the boost voltage to the boost voltage transmission line, and a transistor, which is turned on in response to the transition of the block selecting signal to the non-selecting level so as to supply the supply voltage to the boost voltage transmission line.

Abstract: A pulse-shaping circuit comprises a current limiter, which is connected in parallel with a voltage divider, for limiting a source voltage and enabling first and second voltage signals divided by the voltage divider to be constantly maintained, and an output voltage limiter which is provided to prevent a collector voltage of an output switching transistor from being increased to more than 0.1 V, so that an output pulse signal from an output terminal thereof may be lowered nearly to about 0.1 V when a low input pulse signal is applied to an input terminal thereof.

Abstract: A linear voltage-to-current converter (VIC) 100 for converting a differential input voltage V.sub.D into a differential output current ID is provided. The VIC (100) comprises a main stage (20) and a correction stage (30) having two FET each. Every stage is fed by a separate current source (150, 160). In two nodes (174, 172) the output currents of the stages are added. The scale factors k.sub.1 and k.sub.3 of the FET are coordinated so that distortions are reduced.