Abstract: An integrated circuit driver includes an output stage having source drain paths of PFET and NFET connected in series with each other across DC power supply terminals. A pair of CMOS inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. The inverters include resistors connected to NFET and PFET devices which function as voltage controlled switched capacitors respectively connected in shunt with gate electrodes of the output stage PFET and NFET.

Abstract: The present invention overcomes the disadvantages of the prior art and provides a new temperature compensation trimming technique. Temperature compensated output is provided in a logarithmic voltage output device by the steps of: measuring the resistance of a first resistor, a second resistor, and a third resistor at a first temperature; measuring again the resistances of the first resistor, second resistor, and third resistor at a second temperature; and trimming the drift of the third resistor according to a calculated temperature compensation trim.

Abstract: A level shifting circuit. The gate of the PMOS transistor is coupled to an input terminal, and the source of the PMOS transistor is coupled to a power source. The drain of the NMOS transistor is coupled to the drain of the PMOS transistor. The source of the NMOS transistor is coupled to a reverse input terminal. The gate of the NMOS transistor is coupled to the power source. The reverse logic gate having a first terminal is coupled to the drain of the NMOS transistor and a second terminal is coupled to the output terminal.

Abstract: A differential termination resistor adjusting circuit includes: a reference current producing section that produces a nearly constant reference current Iref, a reference voltage producing section that produces nearly constant reference voltages VrefH, VrefL, a replica resistor producing section that is provided with the reference current Iref to produce voltage drops Va, Vb, a control voltage producing section that produces control voltages Vcont1, Vcont2, based on the reference voltages VrefH, VrefL and the voltage drops Va, Vb, and a genuine resistor producing section that is built in a receiving side device and is connected to an input termination, characterized in that the resistances of the replica resistor producing section and the genuine resistor producing section are adjusted by the control voltages Vcont1, Vcont2.

Abstract: Methods and apparatus are provided for implementing a CMOS low voltage current source. The current source embodies a voltage feedback mechanism with a low voltage gain. The current source controls a gate of an output driver FET such that a substantially constant current is maintained, even for a portion of the linear range of operation of the output FET. The current source is suitable for driving transmission lines on printed wiring boards, or other application where the load is relatively heavy or complex, and where operation near the power supply is required.

Abstract: A feedback system such as a phase locked loop (PLL) includes a second feedback loop which responds when a VCO control voltage is near either end of its range, by slowly adjusting additional tuning elements which control the VCO frequency. The second feedback loop is arranged to cause a slow enough change in the VCO frequency that the first traditional feedback loop adjusts the control voltage quickly enough in a direction toward its mid-range value to keep the VCO frequency substantially unchanged. The second feedback loop advantageously incorporates one or more digital control signals which preferably change no more than one bit at a time and with a controlled slow ramp rate. As a result, the PLL maintains phase accuracy so that the operation of the PLL, including subtle specifications such as input data jitter tolerance or output jitter generation when used for clock and data recovery applications, is not negatively impacted.

Abstract: An integrated circuit driver includes an output stage having source drain paths of a PFET and NFET connected in series with each other across DC power supply terminals. A pair of inverters simultaneously responsive to a bilevel signal drive gate electrodes of the PFET and NFET. Each inverter includes a pair of switches and a resistor for connecting opposite polarity voltage sources to a separate capacitor connected in shunt with gate electrodes of the PFET and NFET. The inverters, resistors and capacitors prevent the PFET and NFET from being on simultaneously.

Abstract: A circuit and method are disclosed for monitoring the voltage level of an unregulated power supply. The circuit includes a voltage reference circuit for generating a first reference voltage signal and a trim circuit which generates a trimmed reference voltage signal based upon the first reference voltage signal. A comparator compares the unregulated power supply voltage to the trimmed reference voltage signal and asserts an output signal based upon the comparison. The output signal is fed back as an input to the trim circuit so that the trim circuit provides a hysteresis effect.

Abstract: A voltage pump and method of driving a node to an increased potential. A periodic input signal is fed into a precharged small capacitor to create a level shifted periodic intermediate potential at an intermediate node. The intermediate node is a supply node to a level translator circuit. The output of the level translator circuit controls the actuation of a pass transistor. When actuated the pass transistor drives a boosted potential to an output node of the voltage pump circuit. In one embodiment the level translator circuit has a delay element which maintains the deactivation of a pull down portion of the level translator circuit until a pull up portion of the level translator circuit is deactivated. A first diode clamp is used to limit the output of the level translator circuit and the boosted potential to within 1 threshold voltage (of the diode clamp) of each other.

Abstract: A current mirror circuit provides an excellent current that does not deteriorate, even when the power source is a lower supply voltage. A mirror current flows in a first MOS transistor when a constant current flows in the MOS transistor from a current source. A subtracter outputs the difference between voltage Vg1 of the gate of the MOS transistor and voltage Vd1 of the drain, and applies this difference to the gate of a second MOS transistor. When the power-supply voltage of this circuit becomes a lower supply voltage and the absolute value of Vd1 decreases, the MOS transistors enter the triode region, and the mirror current decreases. When the absolute value of Vd1 decreases, because the difference between Vg1 and Vd1 becomes larger, the drain current of the second MOS transistor increases, and the amount by which the mirror current decreases is counterbalanced.

Abstract: A bias generator circuit with improved phase margin without RC compensation includes: a first transistor MP4; a second transistor MP3 coupled in parallel with the first transistor MP4; an amplifier A1 having a first input coupled to the first and second transistors MP4 and MP3, and to a gate of the second transistor MP3, and a second input coupled to a control voltage node VCTRL; a third transistor MN4 coupled in series with the first transistor MP4; a fourth transistor MN2 coupled in series with the third transistor MN4 and having a gate coupled to an output of the amplifier A1; a fifth transistor MP1; a sixth transistor MP2 coupled in parallel with the fifth transistor MP1; a seventh transistor MN3 coupled in series with the fifth transistor MP1; and an eighth transistor MN1 coupled in series with the seventh transistor MN3 and having a gate coupled to a gate of the fourth transistor MN2.

Abstract: An integrated circuit that includes a signal pad, a clamping circuit including a first NMOS transistor having a drain, a source, a gate and a substrate, wherein the drain of the first NMOS transistor is coupled to the signal pad and the source of the first NMOS transistor is coupled to ground, and a control circuit coupled to the gate and substrate of the first NMOS transistor and the signal pad, the control circuit providing a first bias voltage signal to the gate and a second bias voltage signal to the substrate. The voltage level of the first bias voltage signal may be equal to, greater than, or less than the second bias voltage signal. By independently optimizing the trigger levels of the substrate and gate of the transistor in the clamping circuit, a robust ESD protection circuit can be obtained to suit the requirements of different process technologies.

Abstract: A resistance adjustable of resistance mirror circuit having a master resistor R0, a reference current source terminal providing a current value I0 through the master resistor R0 to ground; a first transistor; a current mirror source terminal providing a current value n I0, through the first transistor to ground; an operational amplifier having a positive terminal connecting to a drain of the first transistor, a negative terminal connecting to the other terminal of the master resistor R0, and an output terminal connecting to a gate of the first transistor; a mirror resistor set composed of a plurality of transistors in parallel each other and having their source electrode connecting to ground. Each transistor of the mirror resistor set has a ratio of channel width over channel length being m-fold of that of the first transistor, where m, n is any positive numbers.

Abstract: A system and method to reduce leakage power while minimizing performance penalties and noise is disclosed. In accordance with one embodiment of the invention, the system includes at least one sleep transistor operatively coupleable between a system power supply and at least one circuit powered by the system power supply to control the application of power to the circuit. The sleep transistor is also operatively coupleable to receive a sleep control signal to turn the sleep transistor on and off. A body bias voltage generator is operatively coupleable to a body of the at least one sleep transistor to substantially reduce leakage current when the sleep transistor is non-operational or idle and to improve the operational characteristics of the sleep transistor when the transistor is operational by reducing the performance penalty of the sleep transistor and by reducing impact of noise on the circuit and other devices.

Abstract: A power-on reset (POR) circuit comprises a transistor connected ad diodes for setting temperature time delay coupled to a power supply voltage, a transistor switch, and buffering circuits. The trip point voltage of the POR circuit depends only on one type of transistor, such as the switching transistor so that the p-to-n skew variations do not affect the trip point. The switching transistor has a resistor connected from base to ground and another resistor connected to the power supply voltage to limit current flow during transitions.

Abstract: A charge pump circuit with a small loop filter capacitor is disclosed in the invention. This is accomplished by providing multiple currents which add to the desired current, I. A switching circuit switches one of the currents through the capacitor, while directing a combination of the multiple currents through the resistors. In this way, a smaller current is provided through the capacitor, allowing the capacitor to be much smaller in size.

Abstract: A semiconductor integrated circuit device includes a charge pump circuit for outputting a predetermined negative voltage to a negative voltage node, a voltage detection circuit for generating a first detection signal when the voltage of the negative voltage node has reached a first detection voltage and for generating a second detection signal when the voltage of the negative voltage node has reached a second detection voltage, an oscillator that is driven in response to the first detection signal so as to generate a signal for driving the charge pump circuit, and a negative voltage raising circuit that has an output terminal connected to the negative voltage node, and that is driven in response to the second detection signal so as to raise the voltage of the negative voltage node through the output of its output terminal. The VBB voltage can be increased rapidly and can be controlled at higher speeds, thereby increasing the stability of the voltage.

Abstract: A device which uses a detection circuit to determine whether an output current thereof is source-induced or load-induced, and the method therefor. The device which performs some type of operation based upon the determination as to whether the output current thereof is source-induced or load-induced, and method therefor. The detection circuit determines whether polarities of the output current and an output voltage are the same, and determines the output current to be source-induced if the polarities are the same and load-induced if the polarities are opposite each other. Such a device may have many applications, including use in systems where distinctions between source and load-induced currents are employed in feedback systems to control the system voltage source, systems where the system voltage source is not controlled, but other sources are controlled to influence a summation of voltages and currents at sensing locations, and systems for measurement instrumentation.

Abstract: Devices and method for effectively filtering a signal, particularly for a communication system, are disclosed. In this regard, an exemplary embodiment of the present invention may be construed as an AFE that includes a high-pass receive filter for a communication system. The filter includes an AC-coupled capacitive input and a plurality of RC integrators. At least one of the plurality of RC integrators includes a damping resistor in parallel with a feedback capacitor and a switch for enabling the damping resistor, such that when the damping resistor is enabled, the at least one RC integrator is damped so as to reduce DC instability.

Abstract: Biasing circuitry for generating and maintaining a substantially constant output bias current. Ratios of selected bias currents and selected transistor sizes ensure that a nominal load current is maintained notwithstanding variations in circuit fabrication processes, power supply voltage and operating temperature.