Abstract: An internal power-source potential supply circuit for supplying an internal power-source potential with high accuracy is disclosed. An external power-source potential (VCE) is connected to the source of a PMOS transistor (Q1) having a drain for applying an internal power-source potential (VCI) to a load (11) and a gate receiving a control signal (S1) from a comparator (1). The comparator (1) outputs the control signal (S1) on the basis of a comparison result between a reference potential (Vref) and a divided internal power-source potential (DCI). The drain of the PMOS transistor (Q1) is connected to a first end of a resistor (R1), and a current source (2) is connected between a second end of the resistor (R1) and ground. A voltage provided at a node (N1) serving as the second end of the resistor (R1) is applied to a positive input of the comparator (1) as the divided internal power-source potential (DCI).

Abstract: A temperature compensation circuit for a Hall element has a first and a second band gap reference circuit. The Hall element is fed from an excitation current that is proportional to a first reference voltage produced in the first band gap reference circuit. Furthermore, a second band gap reference circuit has a second resistor of a different resistor type than the first resistor. A second reference voltage is dropped across the second resistor. Inputs of a comparator are connected to the Hall sensor and to the second resistor. The comparator compares the Hall voltage with the second reference voltage. The present temperature compensation circuit automatically compensates for manufacturing-dependent and temperature-dependent tolerances.

Abstract: The present invention comprises a first MOS transistor whose gate and drain are connected with a first node, a second MOS transistor whose gate and drain are connected with the first node and a third node, respectively, a first resistive element which is connected between the first node and a second node, a second resistive element which is connected between the second node and a ground voltage terminal, a first NOT circuit whose input terminal is connected with the second node, whose output terminal is a fourth node, and which is connected between the third node and the ground voltage terminal, and a second NOT circuit whose input terminal is connected with the fourth node and whose output terminal is a fifth node. Consequently, the present invention can detect voltage in a stable condition with low power consumption.

Abstract: A voltage regulator with dynamically boosted bias current includes a pass device for providing current to a load; an error circuit responsive to a difference between a predetermined reference voltage and a function of the voltage on the load to produce an error signal, a driver circuit responsive to the error signal for controlling the pass device to adjust the current to the load to reduce the error signal, the driver circuit including an amplifier responsive to the error signal for controlling the pass device, a bias current source for biasing the amplifier, a sensing circuit for sensing a portion of the error signal, a reference current source for providing a reference current, a second error circuit responsive to a difference between the portion of the error signal and the reference current to produce a second error current; and a boost circuit responsive to the second error signal to increase the bias current provided to the amplifier when the load demands more current.

Abstract: A semiconductor integrated circuit comprises a logic circuit which is formed of p-channel MIS transistors and n-channel MIS transistors, a first oscillation circuit of variable oscillation frequency which is formed of p-channel MIS transistors and n-channel MIS transistors, a control circuit which produces a control signal for controlling the threshold voltage of the p-channel and n-channel MIS transistors, and a second oscillation circuit which produces multiple reference clock signals of different frequencies depending on the operation mode. The control circuit receives a reference clock signal and controls the first oscillation circuit with the control signal so that the oscillation frequency of the first oscillation circuit is correspondent to the frequency of the reference clock signal.

Abstract: A charge pump for negative voltages, having at least one stage including a high-voltage terminal and a low-voltage terminal; a first branch and a second branch, which are symmetrical and are connected between the high-voltage terminal and the low-voltage terminal and each of which comprises a respective first transistor and a respective second transistor. The first and the second transistors are all triple-well MOS transistors of one and the same polarity type.

Abstract: The method includes an adjustment phase in which a filtering device is operated as an oscillator, the frequency of oscillation of the filtering device is determined, and the characteristics of the filtering device are corrected with respect to the determined oscillation frequency and to a pre-established relation between the frequency of oscillation and the theoretical cutoff frequency, in such a way as to confer upon the filtering device a cutoff frequency equal to the theoretical cutoff frequency to within a tolerance. After the adjustment phase, a working phase takes place in which the filtering device carries out its filtering function.

Abstract: An apparatus comprising an input section and an output section. The input section may be configured to generate a first control signal and a second control signal in response to an input signal and a select signal. The output section may be configured to generate an output signal in response to the first and second control signals. The output signal may be (i) related to the input signal when in a first mode and (ii) disabled when in a second mode.

Abstract: A FET square multiplier is disclosed that transforms an input signal into two currents I1 and I2, the difference of which is proportional to the square of the input signal. A first and a second FET are connected at their drains and are source-coupled to the source of a third FET whose transconductance is twice the transconductance of the first and the second FET. The common source node is biased by a constant current source. The FETs are operated in the saturation region to exploit the square dependency of the drain current on the difference of the gate-source voltage and the treshold voltage of an FET.

Abstract: A voltage generation circuit for generating a read-back voltage in response to a supply voltage and a reference voltage. The voltage generation circuit includes a comparator configured to receive the supply voltage and the reference voltage. The voltage generation circuit activates a select signal if the supply voltage has a predetermined relationship with respect to the reference voltage, and de-activates the select signal if the supply voltage does not exhibit the predetermined relationship with respect to the reference voltage. An adjustable voltage divider circuit is coupled to receive the supply voltage and the select signal. The adjustable voltage divider circuit is configured in response to the select signal to provide an output voltage that is a first percentage of the supply voltage if the select signal is activated, and provide an output voltage that is a second percentage of the supply voltage if the select signal is de-activated.

Abstract: A bias generator adjustment system adjusts a PLL or DLL bias generator dependent on negative bias temperature instability effects in an integrated circuit. The bias generator adjustment system uses an aging independent reference circuit and a bias circuit to operatively adjust a bias generator such that transistor ‘aging’ effects that occur over the lifetime of an integrated circuit are compensated for or corrected.

Abstract: The present invention provides a thermal sensor circuit for sensing the temperature of an integrated circuit chip, the thermal sensor circuit including: an output comparator for comparing a reference voltage, Vref, with a sensed voltage, Vsense, the sensed voltage being measured over a sensing resistor relative to the ground potential of the circuit; a first circuit to which a reference voltage line in connected to measure Vref; a first current mirror providing a first current input to the first circuit and to a compensation circuit; and second current mirror providing a second current input to the compensation circuit and to the sensing resistor.

Abstract: A phase lock loop circuit including a voltage controlled oscillator and a phase detector having a sampling circuit and a linear voltage-to-current converter to create a control voltage for the voltage controlled oscillator. The phase lock loop circuit comprising a voltage-to-current circuit to influence a voltage on a capacitor, the voltage controlled oscillator responsive to the voltage on the capacitor, and the sampling circuit responsive to the first and second clock signals to generate two voltage values.

Abstract: A VBB control circuit includes an intermediate potential generation circuit receiving a substrate potential VBB which is a negative potential and outputting a divided potential between a power supply potential INTVDD and a ground potential, and an inverter receiving the divided potential and determining whether the substrate potential is higher or lower than a desired value. A logic threshold value of the inverter is (½)×INTVDD. If a relationship of VBB=VREFB−(½)×INTVDD is satisfied, the divided potential accurately becomes (½)×INTVDD. Thereby, it is possible to realize a semiconductor device including a detection circuit which can arbitrarily select a detected potential of the VBB by changing VREFB and which is less influenced by a change in manufacturing conditions.

Abstract: A low standby current power-on reset circuit is described. A first NMOS transistor's drain is coupled to a first PMOS transistor's drain; source coupled to ground line; and gate coupled to a first capacitor coupled to ground line. The first PMOS transistor's source is coupled to power line; gate coupled to second capacitor coupled to ground line; and drain provides a power-on reset indication. A second PMOS transistor's source is coupled to power line; drain is coupled to drain of second NMOS transistor, gates of first PMOS, second PMOS, and second NMOS transistors, and second capacitor. The second NMOS transistor's source is coupled to gate of first NMOS transistor and first capacitor. A discharge circuit is coupled to power line, ground line, and first and second capacitors for discharging the capacitors when a voltage on power line drops below a level determined by the second PMOS transistor's threshold voltage.

Abstract: A first differential amplifier circuit includes a first P-type transistor and a second P-type transistor which constitute a current mirror circuit, and operates based on an input voltage VIN. A second differential amplifier circuit includes a first N-type transistor and a second N-type transistor forming a current mirror circuit and operates based on the common input voltage VIN. A third P-type transistor operable based on a first signal S1 from the first differential amplifier and a third N-type transistor operable based on a second signal S2 from the second differential amplifier are provided. A voltage between these third P-type and third N-type transistors becomes an output voltage VOUT.

Abstract: An inter-stage matching circuit 26 comprises a one-stage high pass filter type matching unit 28 and a one-stage low pass filter type matching unit 29 serially connected with each other.

Abstract: A power control circuit includes sensing circuitry for sensing information about operation of a power device such as an IGBT or other power FET. The sensing circuitry receives a sense input signal from the power device through a gating device such as a diode. The power control circuit also includes active impedance circuitry for preventing the sense input signal from including spurious information received from the gating device. For example, if the gating device is a diode across which negative spikes can be capacitively coupled, the active impedance circuitry can prevent the negative spikes from reaching the sensing circuitry when the diode is off. The active impedance circuitry can take the form of a transistor connected between a power supply and a sensing node. The active impedance device can be switched on by a comparator when the voltage across the power device exceeds a reference voltage, indicating the power device is off.

Abstract: An IC device has a MOSFET serving as a power switch, a condenser connected between a first input terminal of the IC and the gate of the MOSFET, and a ferroelectric condenser connected between a second input terminal of the IC and the gate of the MOSFET. A prescribed voltage having a predetermined polarity is applied across the first and the second input terminals to generate a remanent polarization oriented in a specific direction in the ferroelectric condenser, thereby raising the threshold voltage of the MOSFET to a higher level than its original level. The power switching MOSFET is fabricated in the same manufacturing process as for other circuit blocks of the IC device such that it has substantially the same threshold voltage as that of the MOSFETs in other circuit blocks.

Abstract: A system on a chip (SOC voltage generator) system is provided for supplying at least one voltage level to a plurality of units on a chip having an SOC design. The system includes a plurality of local DC voltage generators distributed throughout the chip, each local DC voltage generator independently supplying voltage to at least one unit of the plurality of units, each local DC voltage generator including a regulator system outputting one pump control signal; and a pump system receiving the one pump control signal and outputting at least one voltage level in accordance with the one pump control signal. Furthermore a method for supplying voltage to a plurality of units on a chip having an SOC design is provided. The method includes the steps of distributing a plurality of local DC voltage generators throughout the chip; and supplying at least one voltage level to the plurality of units via the plurality of local DC voltage generators.