Patents Examined by Terry D. Cunningham
  • Signaling accommodation
    Patent number: 6876248
    Abstract: A receiving unit may implement voltage compensation using a parameters table, an analog calibration component, and/or a digital calibration component. In certain implementation(s), an integrated circuit may include a voltage driver that modifies a supplied compensated voltage based on a feedback signal. The feedback signal may be produced responsive to a distributed voltage version of the compensated voltage, to a received data signal, and to a comparison involving an expected data value. In other implementation(s), a parameters table may be initialized by storing calibration values in entries in association with respective multiple identifications of multiple external points.
    Type: Grant
    Filed: May 28, 2002
    Date of Patent: April 5, 2005
    Assignee: Rambus Inc.
    Inventors: Huy M. Nguyen, Benedict C. Lau
  • Compact DC stabilized power supply capable of suppressing fluctuation of output voltage in spite of abrupt fluctuation of load current
    Patent number: 6873204
    Abstract: A DC stabilized power supply 10 for converting an inputted DC power supply voltage into a predetermined DC voltage includes a converting circuit 11, a first differentiating circuit 12 for differentiating variations in an output voltage of the converter circuit 11, a current absorbing circuit 13 driven by an output voltage of the first differentiating circuit 12, a second differentiating circuit 14 for differentiating variations in the output voltage of the converter circuit 11, and a current injecting circuit 15 driven by an output voltage of the second differentiating circuit 14.
    Type: Grant
    Filed: October 12, 2001
    Date of Patent: March 29, 2005
    Assignee: NEC Corporation
    Inventor: Eishi Matsuda
  • Tunable quadrature phase shifter
    Patent number: 6873198
    Abstract: The present invention relates to a tunable quadrature phase shifter comprising an input (IN) for inputting an input signal (vin), splitting means (10) for splitting the input signal into two essentially orthogonal first and second signals (i1, i2), adding means (6) for adding said first and second signals (i1, i2), subtracting means (7) for subtracting said first and second signals (i1, i2), a first output (OUT+) for outputting a first output signal (vo1) based on the output signal from said adding means (6), and a second output (OUT?) for outputting a second output signal (vo2) based on the output signal from said subtracting means (7), wherein that said splitting means (10) is provided as an all-pass.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: March 29, 2005
    Inventor: Mihai Adrian Tiberiu Sanduleanu
  • Power-up detection apparatus
    Patent number: 6873192
    Abstract: A power-up detection apparatus comprises a voltage divider, a potential detector and a buffer. The voltage divider divides an inputted power voltage in a predetermined ratio. The potential detector compares a predetermined potential with a potential outputted from said voltage divider, and outputs the comparison result. The buffer changes the level of said comparison result when said comparison result outputted from said potential detector is maintained at a predetermined potential for a predetermined period. As a result, a semiconductor device can be stably initialized because a power-up signal is generated only when an externally inputted power voltage is maintained at a current state over a predetermined period although the state of the external power voltage is toggled by noise.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 29, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventors: Chang Seok Kang, Jae Jin Lee
  • Method of increasing an internal operating voltage for an integrated circuit, and integrated circuit
    Patent number: 6870420
    Abstract: An increased internal operating voltage for an integrated circuit can be generated with two two-stage charge pumps, ensuring reliable operation even in the event of an external voltage supply Vext=1.8 V or less. The two charge pumps cooperate with a common first stage in a cyclic sequence. A temporally offset organization of the cycles of the two charge pumps enables operation in a manner that is free from disturbances. Moreover, the large chip area required for capacitors can advantageously be considerably reduced.
    Type: Grant
    Filed: May 5, 2003
    Date of Patent: March 22, 2005
    Assignee: Infineon Technologies AG
    Inventors: Michael Hausmann, Joachim Schnabel
  • Receiving circuit
    Patent number: 6867623
    Abstract: A receiving circuit including an amplifier for generating a receiving voltage signal, a comparator for generating a binary signal from the receiving voltage signal, and a logic maintaining circuit for receiving the binary signal and maintaining the binary signal at a shifted level for a predetermined period after the level of the binary signal is shifted. The logic maintaining circuit prevents noise pulses from appearing in a receiving signal.
    Type: Grant
    Filed: October 24, 2002
    Date of Patent: March 15, 2005
    Assignee: Fujitsu Limited
    Inventor: Kazunori Nishizono
  • Low noise resistorless band gap reference
    Patent number: 6864741
    Abstract: The junction difference used for a band gap voltage reference is designed so that it has the needed temperature coefficient without amplification. This is accomplished by the appropriate choice of the number of junctions and the appropriate current densities. Only one polarity of bipolar transistors is required. The noise terms of each junction add in root mean square, rather than be linear amplification, resulting in a lower noise reference than other designs requiring only a single type of bipolar transistors. By using metal available in standard integrated circuit processes to form a resistor, a low temperature coefficient current source can easily be obtained.
    Type: Grant
    Filed: December 9, 2002
    Date of Patent: March 8, 2005
    Inventors: Douglas G. Marsh, Apparajan Ganesan
  • Charge pump with Fibonacci number multiplication
    Patent number: 6861894
    Abstract: A charge pump includes a plurality of capacitors that are alternately charged and serially coupled. When serially coupled, the voltage across a given capacitor will equal the voltage at its negative terminal and the voltage across the preceding capacitor.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: March 1, 2005
    Assignee: SanDisk Corporation
    Inventor: Raul-Adrian Cernea
  • Leak current compensating device and leak current compensating method
    Patent number: 6856190
    Abstract: To provide a leak current compensating device which ensures that the voltage of the output terminal is made to ground potential while minimizing sink current flowing from the output terminal, when the output transistor goes into the OFF state.
    Type: Grant
    Filed: October 30, 2003
    Date of Patent: February 15, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventor: Hideyuki Kihara
  • Bandgap reference source
    Patent number: 6853238
    Abstract: The invention describes a bandgap reference circuit that may be configured to provide a reference current or voltage as an output thereof. The output may be provided in the form of a constant source, or one including PTAT or CTAT dependencies. The circuit utilises a single amplifier whose output is coupled to a current control block which is then used to drive a dual feedback loop of the amplifier. Inputs to the amplifier are directly coupled to reference nodes in a manner which establishes a PTAT voltage across a resistor at an input of the amplifier.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: February 8, 2005
    Assignee: Analog Devices, Inc.
    Inventors: Dennis A. Dempsey, Stefan Marinca
  • Charge pump circuit
    Patent number: 6850111
    Abstract: A charge pump circuit provides an output voltage greater than a supply voltage of the charge pump circuit. The charge pump circuit has a first and a second charge storage device driven and connected up to one another such that the output voltage is higher than the dielectric strength of the individual capacitors. Switching devices are alternately switched on and off dependent on a high-frequency signal, so that the first charge storage device is charged during a first clock phase and the charge of the first charge storage device is transferred to the second charge storage device during a second clock phase. The charge pump circuit is distinguished by a low current demand, high output voltages and the provision of an output voltage with a low internal resistance. In a preferred embodiment, the switching devices have bipolar transistors, equipped with anti-saturation circuits.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: February 1, 2005
    Assignee: Infineon Technologies AG
    Inventor: Udo Ausserlechner
  • Device for controlling a circuit generating reference voltages
    Patent number: 6850112
    Abstract: Control device for a generation circuit (REF) for reference voltages (VPOL1, VPOL2), includes a first P type MOS transistor (M12), connected between a node (N) to which a high voltage signal (EHV) is applied and a first intermediate node (A), a second P type MOS transistor (M13) connected between the first intermediate node (A) and a second intermediate node (B), and a third P type MOS transistor (M14) connected between the second node and the ground and with its grid connected to its drain, to supply a reference voltage (VPOL1, VPOL2) on one of the first and second intermediate nodes (A, B). The control device includes a controlling mechanism for controlling the reference transistors, either in a first or second operating mode.
    Type: Grant
    Filed: January 23, 2002
    Date of Patent: February 1, 2005
    Assignee: STMicroelectronics S.A.
    Inventor: Cyrille Dray
  • Method for nulling charge injection in switched networks
    Patent number: 6850098
    Abstract: A system and method to overcome or nullify a charge injection and clock feed-through error voltage caused by the turning-off charge of a switched element(s) in switched networks. A circuit for nulling a charge injection and clock feed-through error voltage includes, for example, two switched elements and a capacitor. The circuit can be used to replace any switch element in a switched network. The circuit may also include, for example, three switched elements and two capacitors.
    Type: Grant
    Filed: July 27, 2001
    Date of Patent: February 1, 2005
    Assignee: Nanyang Technological University
    Inventors: Wing Foon Lee, Pak Kwong Chan
  • Sub-micron high input voltage tolerant input output (I/O) circuit which accommodates large power supply variations
    Patent number: 6847248
    Abstract: A method of providing bias voltages for input output connections on low voltage integrated circuits. As integrated circuit voltages drop generally so does the external voltages that those circuits can handle. By placing input and output devices, in series, external voltages can be divided between the devices thereby reducing junction voltages seen by internal devices. By using external voltages as part of a biasing scheme for integrated circuit devices, stress created by the differential between external voltages and internal voltages can be minimized. Additionally device wells can be biased so that they are at a potential that is dependent on the external voltages seen by the low voltage integrated circuit.
    Type: Grant
    Filed: January 9, 2002
    Date of Patent: January 25, 2005
    Assignee: Broadcom Corporation
    Inventor: Janardhanan S. Ajit
  • Pumping circuit for outputting program voltage and program verify voltage of different levels
    Patent number: 6847250
    Abstract: The present invention relates to a pumping circuit. The pumping circuit comprises a first pumping block for pumping an input voltage, a first latch for latching the output of the first pumping block, a second pumping block for pumping the output of the first pumping block according to a control signal, a second latch for latching the output of the second pumping block, and a switching circuit for selectively outputting the outputs of the first and second latches according to the control signal. Thus, a program voltage and a program verify voltage of different levels are pumped. The ripple and active current can be reduced and the program efficiency can be increased.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: January 25, 2005
    Assignee: Hynix Semiconductor Inc.
    Inventor: Young Joo Kim
  • Threshold voltage extraction circuit
    Patent number: 6844772
    Abstract: A threshold voltage extraction circuit. The circuit includes a first current mirror having a first transistor and a second transistor. A holding circuit has an output adapted to control a current though the first current mirror by operating to maintain substantially equal the voltages at a first input thereof and at a second input thereof. A third, MOS transistor having a source and a gate, and a resistor circuit, together adapted to generate a voltage which is a multiple of a source-gate threshold voltage of the third transistor, are coupled to the second transistor and to the first input of the holding circuit. A fourth, MOS transistor coupled to the first transistor and to the second input of the subtracting circuit through a second resistor circuit is adapted to generate a threshold voltage across the second resistor circuit, by the operation of the holding circuit.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: January 18, 2005
    Assignee: Texas Instruments Incorporated
    Inventors: Siew Kuok Hoon, Jun Chen
  • Electrical fuse programming control circuit
    Patent number: 6842065
    Abstract: An electrical fuse programming control circuit includes a plurality of fuse blocks each having a plurality of electrical fuses and an end fuse block. When all of the fuse blocks are programmed, the end fuse block is enabled and generates a programming control signal. The electrical fuse programming control circuit also includes a comparing unit that selectively transmits a fuse cutting signal to the plurality of fuse blocks in response to the programming control signal from the end fuse block. When programming of all of the fuse blocks is complete, reprogramming of the fuse blocks is not performed when an illegal program command is provided as an input.
    Type: Grant
    Filed: December 30, 2002
    Date of Patent: January 11, 2005
    Assignee: Hynix Semiconductor, Inc.
    Inventor: Jong Tai Park
  • Method and system for signal dependent boosting in sampling circuits
    Patent number: 6833753
    Abstract: A system for signal boosting includes a capacitance boosting component that contains a first and second transistor and a capacitor, wherein a positive terminal of the capacitor is electrically connected to a drain of the second transistor and a negative terminal of the capacitor is electrically connected to a source of the first transistor. The system also includes a third transistor operable to receive a clock signal. A drain of the third transistor is electrically connected to the positive terminal of the capacitor. A fourth transistor is operable to receive an inverse of the clock signal. A drain of the fourth transistor is electrically connected to the positive terminal of the capacitor. The system further includes a boost component electrically connected to the capacitance boosting component wherein an output of the boost component is within a selected boost voltage range.
    Type: Grant
    Filed: November 27, 2002
    Date of Patent: December 21, 2004
    Assignee: Texas Instruments Incorporated
    Inventor: Mrinal Das
  • Circuit for controlling an initializing circuit in a semiconductor device
    Patent number: 6833741
    Abstract: A circuit for controlling an initializing circuit in a semiconductor device is described herein. The circuit comprises a first circuit configured to generate a NOP operation command signal, and a second circuit configured to maintain a power-up signal to a LOW state until the NOP operation starts and to shift the power-up signal to a HIGH state based on the NOP operation command signal.
    Type: Grant
    Filed: December 23, 2002
    Date of Patent: December 21, 2004
    Assignee: Hynix Semiconductor Inc.
    Inventor: Nak Kyu Park
  • Current or voltage generator with a temperature stable operating point
    Patent number: 6831503
    Abstract: A current or voltage generator is integrated onto a silicon wafer and may include a first element including a first NMOS transistor having its source connected to ground through an electrical resistance, a second element including a second NMOS transistor having its source connected to ground, and a bias circuit for the first and second elements. The second element may include a voltage divider. The gate of the second NMOS transistor may be connected to a dividing node of the voltage divider, and the anode of the voltage divider may be connected to the gate of the first NMOS transistor. Both elements may be biased at an operating point corresponding to an identical temperature stability point for both elements.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: December 14, 2004
    Assignee: STMicroelectronics SA
    Inventor: Francesco La Rosa