Abstract: A dual output voltage regulator circuit includes a first voltage regulator section, the first voltage regulator section having a first regulated voltage output, a second voltage regulator section coupled to the first voltage regulator section, the second voltage regulator having a second regulated voltage output, and a switching circuit coupled to the first voltage regulator section and to the second voltage regulator section, the switching circuit operating the first voltage regulator section and the second voltage regulator section in a normal mode, and operating only the second voltage regulator section in a power gating mode.

Abstract: In a packaged integrated circuit, the package inductance limits the rate at which off-chip current may be varied in response to a change in on-chip current demand of the integrated circuit. The present invention provides an on-chip voltage regulator circuit for regulating multi-cycle voltage fluctuations of an integrated circuit associated with changes in current demand of the integrated circuit. The voltage regulator sources current to prevent an undervoltage conditions and sinks current to prevent an overvoltage condition.

Abstract: In a circuit including a number of functional blocks of circuits, each block having a minimum operating voltage, a plurality of sense lines from each of the blocks is used to measure local voltage fluctuation at each block. The power voltage(s) of the overall circuit may be globally regulating in the circuit responsive to such locally sensed voltage fluctuations to prevent the local voltages from dropping below the minimum operating voltage for each block.

Abstract: A fast start-up low-voltage bandgap voltage reference circuit is disclosed. The bandgap voltage reference circuit includes: a first current generator, which is implemented by a self-bias unit and a current mirror for generating a first reference current with positive temperature coefficient; a second current generator, which is connected to a point with negative temperature coefficient in the first current generator to generate a second reference current with negative temperature coefficient; and a resistor for converting the first reference current and the second reference current into a low-voltage bandgap voltage independent of temperature. Because the bandgap voltage reference circuit of the invention uses the resistor to convert the first reference current and the second reference current into voltage, the circuit can provide low-voltage bandgap voltage.

Abstract: A semiconductor integrated circuit device having an internal voltage generating circuit which generates a voltage two or more times higher than an operating voltage while at the same time reducing the voltage applied to a device, thereby ensuring the device reliability. In a charge pump circuit driven by supply voltage VDD, a maximum of 2 VDD or a similar level voltage is applied between the drain and source of a MOSFET, the MOSFET being connected in series with a conduction MOSFET of the same type, the gate of which is supplied with VD?VDD, or a potential which is VDD lower than VD, the drain potential before its connection. The gate potential is obtained directly from a node in said charge pump which generates a voltage pulse synchronized with the voltage between the drain and source of that MOSFET, or through another rectifier device branched via a capacitor from the node.

Abstract: A regulated charge pump has a negative charge pump for generating a first output voltage according to an oscillation signal, and a regulator. The regulator has a level shift circuit, a differential amplifier for generating a compare signal, and an oscillator for generating the oscillation signal according to the compare signal. The level shift circuit has a plurality serially connected PMOS transistors. A first PMOS transistor has a first source connected to a first reference voltage, and a gate and a drain both connected to an output end of the level shift circuit. A second PMOS has a gate and a drain both connected to an output end of the negative charge pump.

Abstract: Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide circuit configurations. The output buffer is adapted to couple to separate voltage supply voltage level ports and is further adapted to switch between the circuit configurations. The respective circuit configurations are respectively specifically adapted for interoperating with other integrated circuit chips, the respective threshold voltage levels of the semiconductor devices of different other integrated circuit chips being different.

Abstract: A multimode voltage regulator includes a low current pass device and a high current pass device each adapted for connection between a power supply and a load; an error amplifier responsive to a difference between a reference voltage and a function of the voltage on the load to produce an error signal; and a low power driver responsive in a low load power mode to an error signal for operating the low current pass device to provide low power to the load and a high power driver responsive in a high load power mode to an error signal for operating the high current pass device to provide high power to the load for maintaining efficiency over high and low power load operation.

Abstract: A semiconductor booster circuit is disclosed that boosts a power-supply voltage to approximately twice the original voltage. When a reference clock signal is at the ground voltage, an inverted clock signal becomes the power-supply voltage, and the power-supply voltage is conducted from the power supply input terminal by way of a third FET transistor and stored in a first capacitor, and the stored voltage of a second capacitor is delivered from an external output terminal by way of a second FET transistor. Conversely, when the reference clock signal is at the power-supply voltage, the power-supply voltage is conducted from the power supply input terminal by way of a fourth FET transistor and stored in the second capacitor, and the stored voltage of the first capacitor is delivered from the external output terminal by way of the first FET transistor.

Abstract: An integrated circuit has one or more components that operate with reference to a distributed reference voltage. A reference voltage driver produces a compensated reference voltage, and the compensated reference voltage is distributed to form the distributed reference voltage at the components. Due to factors such as trace resistance and gate leakage, the distributed reference voltage is degraded relative to the compensated reference voltage. The reference voltage driver is responsive to feedback derived from the distributed reference voltage to adjust the compensated reference voltage so that the distributed reference voltage is approximately equal to a nominal reference voltage.

Abstract: A current mirror circuit that provides an excellent current that does not deteriorate, even when the power source is lower supply voltage. A mirror current flows in a first MOS transistor when a constant current flows in the MOS transistor from a current source. A subtracter outputs the difference between voltage Vg1 of the gate of the MOS transistor and voltage Vd1 of the drain, and applies this difference to the gate of a second MOS transistor. When the power-supply voltage of this circuit becomes lower supply voltage and the absolute value of Vd1 decreases, the MOS transistors enter the triode region, and the mirror current decreases. when the absolute value of Vd1 decreases, because the difference between Vg1 and Vd1 becomes larger, the drain current of the second MOS transistor increases, and the amount by which the mirror current decreases is counterbalanced.

Abstract: An integrated circuit formed on a semiconductor chip, comprising a low pass filter circuit having a first resistor of a first resistance value and a capacitor of a first capacitance value, wherein the first resistance value and the first capacitance value determine a corner frequency of the filter; and a tuning circuit having a second resistor of a second resistance value, a switched-capacitor of a third resistance value and a comparator that compares two voltage signals to produce a control signal, wherein the control signal adjusts the first and second resistance values as a function of the third resistance value. The corner frequency of the filter can be adjusted by varying one or more reference voltage signals. In combination, the corner frequency of the filter is adjusted by changing the frequency of a clock that controls the switched-capacitor to decrease the circuit sensitivity.

Abstract: An output buffer circuit has a main driver including a first pMOS transistor and a first nMOS transistor for driving a load, and a second pMOS transistor and a second nMOS transistor for driving the load in coaction with the first pMOS transistor and the first nMOS transistor, and a predriver including a third pMOS transistor and a third nMOS transistor for driving the first pMOS transistor, a fourth pMOS transistor and a fourth nMOS transistor for driving the first nMOS transistor, a fifth nMOS transistor for driving the first pMOS transistor in coaction with the third nMOS transistor, and a fifth pMOS transistor for driving the first nMOS transistor in coaction with the fourth pMOS transistor.

Abstract: A method of providing multiple voltage outputs includes receiving an input signal from a multifunctional pump. The method also includes sending a first output signal based on the input signal using a first switch and sending a second output signal based on the input signal using a second switch and a transistor.

Abstract: A mobility proportion current generator comprises a voltage adder including a first MOS transistor, the voltage adder adding a voltage whose temperature dependency is small with respect to the mobility and a threshold voltage of the first MOS transistor to output a sum voltage, and a second MOS transistor including whose drain terminal is connected to a constant potential point, the sum voltage of the voltage adder being applied between the gate terminal and the source terminal of the second MOS transistor to output a current proportional to the mobility being output from the drain terminal thereof.

Abstract: A substrate bias generator which makes device characteristics stable by supplying a predetermined negative voltage to a substrate and minimally reduces current consumption during a self refresh mode. The substrate bias generator comprises a substrate voltage level detector for inputting a substrate voltage and outputting a signal which drives an oscillator in response to the input level, and a controller for inputting a chip active enable signal, a self refresh mode enable signal and an output signal of the substrate voltage level detector and controlling a switching operation of the substrate voltage level detector in response to the input level.

Abstract: Each of a plurality of driving circuits constituting a constant current driving apparatus is composed of a first current mirror circuit and a second current mirror circuit. The first current mirror circuit outputs a plurality of output currents, each of which corresponds to a reference current. Accordingly, the variation in the output current can be reduced between the driving circuits adjacent to each other.

Abstract: An adjustable voltage reference circuit (14, 25, 70) that can be adjusted via an external device is disclosed. The circuit is designed to receive, after packaging, a plurality of adjustment inputs (20). These inputs are used by an adjustable voltage cell (21, 26, 71) to produce an adjustment factor. The adjustment factor will then be used by a voltage reference cell (22, 27, 72) to adjust the reference voltage (Vref).

Abstract: Provided is a high voltage generator including a level detector for selecting one of a plurality of voltage sources in accordance with an option control signal and comparing the selected voltage source with a Vpp voltage; a first oscillator for generating a plurality of pulse signals having different periods, the first oscillator being operated in accordance with the option control signal; a second oscillator for generating pulse signals, the second oscillator operated in accordance with the option control signal; a first charge pump for generating the Vpp voltage by performing a pumping operation in accordance with an output of the first oscillator, the first charge pump being enabled in accordance with the option control signal; and a second charge pump for generating the Vpp voltage by performing a pumping operation in accordance with an output of the second oscillator, the second charge pump being enabled in accordance with the option control signal.

Abstract: A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i.e., the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one ?W. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e.g., the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i.e., frequency, so that the chip will not overheat.