Patents Examined by Thanh Nguyen
  • Patent number: 10085066
    Abstract: A method for communication is described. The method includes providing a channel configured for collecting and editing video associated with a topic. The method includes identifying a plurality of potential parties connected with the topic. The method includes pushing a plurality of invitations to the plurality of potential parties, wherein each invitation comprises a request to join the channel. The method includes receiving a plurality of video feeds on the channel from a plurality of contributors each accepting a corresponding invitation. The method includes editing the plurality of video feeds to generate an edited video.
    Type: Grant
    Filed: March 27, 2017
    Date of Patent: September 25, 2018
    Assignee: NBCUniversal Media, LLC
    Inventor: Philip Groman
  • Patent number: 10076842
    Abstract: Described are machine vision systems and methods for simultaneous kinematic and hand-eye calibration. A machine vision system includes a robot or motion stage and a camera in communication with a control system. The control system is configured to move the robot or motion stage to poses, and for each pose: capture an image of calibration target features and robot joint angles or motion stage encoder counts. The control system is configured to obtain initial values for robot or motion stage calibration parameters, and determine initial values for hand-eye calibration parameters based on the initial values for the robot or motion stage calibration parameters, the image, and joint angles or encoder counts. The control system is configured to determine final values for the hand-eye calibration parameters and robot or motion stage calibration parameters by refining the hand-eye calibration parameters and robot or motion stage calibration parameters to minimize a cost function.
    Type: Grant
    Filed: September 28, 2016
    Date of Patent: September 18, 2018
    Assignee: Cognex Corporation
    Inventors: Lifeng Liu, Cyril C. Marrion, Tian Gan
  • Patent number: 10068616
    Abstract: According to one implementation, a video processing system for performing thumbnail generation includes a computing platform having a hardware processor and a system memory storing a thumbnail generator software code. The hardware processor executes the thumbnail generator software code to receive a video file, and identify a plurality of shots in the video file, each of the plurality of shots including a plurality of frames of the video file. For each of the plurality of shots, the hardware processor further executes the thumbnail generator software code to filter the plurality of frames to obtain a plurality of key frame candidates, determine a ranking of the plurality of key frame candidates based in part on a blur detection analysis and an image distribution analysis of each of the plurality of key frame candidates, and generate a thumbnail based on the ranking.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: September 4, 2018
    Assignee: Disney Enterprises, Inc.
    Inventors: Miquel Angel Farre Guiu, Aljoscha Smolic, Marc Junyent Martin, Asier Aduriz, Tunc Ozan Aydin, Christopher A. Eich
  • Patent number: 10038921
    Abstract: A system, method, and software for mobile video display and management includes acquiring a plurality of streams of video data from a plurality of cameras. The plurality of streams of video data are stored and plurality of selected streams of video data that includes at least one stream of recorded video data and at least one stream of live video data are presented in a graphical user interface of a remote device.
    Type: Grant
    Filed: September 1, 2016
    Date of Patent: July 31, 2018
    Assignee: Verint Systems Ltd.
    Inventors: Royee Goldberg, Yehonatan Farin
  • Patent number: 10017117
    Abstract: A vehicle occupant viewing system and a corresponding method for displaying a vehicle occupant on an image display unit. The system may comprise one or more vehicle interior cameras for obtaining occupant images of one or more occupants in rear seats of the vehicle. The system may include two vehicle interior cameras, one in a forward facing orientation and another in a rear facing orientation, which can capture occupant images of occupants in forward facing positions and occupants in rear facing positions such as infants in car seats. The system may also include one or more modular vehicle interior cameras that are moveable between various orientations in order to capture occupant images of either forward or rear facing passengers. Adjustments can be made to display the occupant images to the driver in a more intuitive arrangement.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: July 10, 2018
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventors: Allan K. Lewis, Michael T. Chaney, Jr., Mohammad Naserian
  • Patent number: 10008000
    Abstract: Systems, methods, apparatus, and computer-implemented methods are provided for determining a camera calibration. The method includes accessing video data for a geographic area captured by a video camera. The video data is processed to detect a plurality of moving vehicles in the video data. A detection area is defined based on the plurality of moving vehicles. A plurality of line segments are identified for each of the plurality of vehicles detected in the video data. A plurality of vanishing points are estimated based on at least a subset of the plurality of line segments. A camera calibration is determined based on the plurality of vanishing points.
    Type: Grant
    Filed: May 18, 2016
    Date of Patent: June 26, 2018
    Assignee: Conduent Business Services, LLC
    Inventors: Hao Wu, Robert P. Loce
  • Patent number: 9136298
    Abstract: Embodiments of mechanisms of for forming an image-sensor device are provided. The image-sensor device includes a substrate having a front surface and a back surface. The image-sensor device also includes a radiation-sensing region operable to detect incident radiation that enters the substrate through the back surface. The image-sensor device further includes a doped isolation region formed in the substrate and adjacent to the radiation-sensing region. In addition, the image-sensor device includes a deep-trench isolation structure formed in the doped isolation region. The deep-trench isolation structure includes a trench extending from the back surface and a negatively charged film covering the trench.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: September 15, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jeng-Shyan Lin, Dun-Nian Yaung, Jen-Cheng Liu, Feng-Chi Hung
  • Patent number: 9082993
    Abstract: OLEDs having increased illumination are disclosed. The OLEDs have light emitting layers with periodic grain sizes. In particular, by depositing smaller particles at the boundaries of the emitting layers, the injection rate of carriers is improved in the emitting layers and by depositing larger particles in the middle of the emitting layers, the carrier density is increased, which increases electron-hole recombination. Increased recombination facilitates radiative emission of exitons from the OLED. As a result of the periodic grain size structure of the emitting layers, the electroluminescence and durability of the OLEDs are improved.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: July 14, 2015
    Inventors: Ezeddin Mohajerani, Jalal Jafari
  • Patent number: 9041214
    Abstract: Methods of fabricating semiconductor structures include implanting atom species into a carrier die or wafer to form a weakened region within the carrier die or wafer, and bonding the carrier die or wafer to a semiconductor structure. The semiconductor structure may be processed while using the carrier die or wafer to handle the semiconductor structure. The semiconductor structure may be bonded to another semiconductor structure, and the carrier die or wafer may be divided along the weakened region therein. Bonded semiconductor structures are fabricated using such methods.
    Type: Grant
    Filed: May 22, 2013
    Date of Patent: May 26, 2015
    Assignee: SOITEC
    Inventors: Mariam Sadaka, Ionut Radu
  • Patent number: 9012921
    Abstract: A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling layer is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling layer is formed by roughening a buffer layer of the light emitting device. The light emitting device includes an electrode in electrical communication with one of the first layer and the second layer through a portion of the light coupling layer.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: April 21, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Chao-Kun Lin, Li Yan, Chih-Wei Chuang
  • Patent number: 9000584
    Abstract: The mechanisms of forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP) are provided. The mechanisms involve covering portions of surfaces of an insulating layer surrounding a contact pad. The mechanisms improve reliability of the package and process control of the packaging process. The mechanisms also reduce the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. The mechanisms further improve planarization end-point. By utilizing a protective layer between the contact pad and the insulating layer, copper out-diffusion can be reduced and the adhesion between the contact pad and the insulating layer may also be improved.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Nai-Wei Liu, Yi-Chao Mao, Wan-Ting Shih, Tsan-Hua Tung
  • Patent number: 8993453
    Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Jeong Byun, Sagy Levy
  • Patent number: 8987029
    Abstract: A method of protecting a substrate during fabrication of semiconductor, MEMS devices. The method includes application of a protective thin film which typically has a thickness ranging from 3 angstroms to about 1,000 angstroms, wherein precursor materials used to deposit the protective thin film are organic-based precursors which include at least one fluorine-comprising functional group at one end of a carbon back bone and at least one functional bonding group at the opposite end of a carbon backbone, and wherein the carbon backbone ranges in length from 4 carbons through about 12 carbons. In many applications at least a portion of the protective thin film is removed during fabrication of the devices.
    Type: Grant
    Filed: November 1, 2011
    Date of Patent: March 24, 2015
    Assignee: Applied Microstructures, Inc.
    Inventors: Jeffrey D. Chinn, Boris Kobrin, Romuald Nowak
  • Patent number: 8981424
    Abstract: A semiconductor device includes a transistor having a gate electrode, a first electrode, and a second electrode and first and second protection circuits each having one end commonly connected to the gate electrode and the other end connected to the first and second electrodes, respectively. The first and second protection circuits are formed in first and second polysilicon layers, respectively, formed separately on a single field insulating film.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: March 17, 2015
    Assignee: Renesas Electronics Corporation
    Inventor: Takayoshi Andou
  • Patent number: 8981495
    Abstract: A transistor includes a substrate, a gate over the substrate, a source and a drain over the substrate on opposite sides of the gate, a first silicide on the source, and a second silicide on the drain. Only one of the drain or the source has an unsilicided region adjacent to the gate to provide a resistive region.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: March 17, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Harry-Hak-Lay Chuang, Lee-Wee Teo, Ming Zhu
  • Patent number: 8970014
    Abstract: Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.
    Type: Grant
    Filed: September 6, 2013
    Date of Patent: March 3, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-jin Lim, Hyung-Suk Jung, Yun-Ki Choi
  • Patent number: 8963162
    Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A carrier channel is located between the first III-V compound layer and the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer. Each of the source feature and the drain feature comprises a corresponding intermetallic compound at least partially embedded in the second III-V compound layer. Each intermetallic compound is free of Au and comprises Al, Ti or Cu. A p-type layer is disposed on a portion of the second III-V compound layer between the source feature and the drain feature. A gate electrode is disposed on the p-type layer. A depletion region is disposed in the carrier channel and under the gate electrode.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: February 24, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Hsu, Jiun-Lei Jerry Yu, Fu-Wei Yao, Chen-Ju Yu, Po-Chih Chen, King-Yuen Wong
  • Patent number: 8940645
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: January 27, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Patent number: 8938603
    Abstract: According to an embodiment of the invention, cache management comprises maintaining a cache comprising a hash table including rows of data items in the cache, wherein each row in the hash table is associated with a hash value representing a logical block address (LBA) of each data item in that row. Searching for a target data item in the cache includes calculating a hash value representing a LBA of the target data item, and using the hash value to index into a counting Bloom filter that indicates that the target data item is either not in the cache, indicating a cache miss, or that the target data item may be in the cache. If a cache miss is not indicated, using the hash value to select a row in the hash table, and indicating a cache miss if the target data item is not found in the selected row.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: January 20, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jonathan M. Haswell
  • Patent number: 8928125
    Abstract: Methods of fabricating a capped interconnect for a microelectronic device which includes a sealing feature for any gaps between a capping layer and an interconnect and structures formed therefrom. The sealing features improve encapsulation of the interconnect, which substantially reduces or prevents electromigration and/or diffusion of conductive material from the capped interconnect.
    Type: Grant
    Filed: September 23, 2011
    Date of Patent: January 6, 2015
    Assignee: Intel Corporation
    Inventors: Jun He, Kevin J. Fischer, Ying Zhou, Peter K. Moon