Patents Examined by Thanh Nguyen
  • Patent number: 8669651
    Abstract: A device includes a package substrate including a first non-reflowable metal bump extending over a top surface of the package substrate; a die over and bonded to the package substrate; and a package component over the die and bonded to the package substrate. The package component includes a second non-reflowable metal bump extending below a bottom surface of the package component. The package component is selected from the group consisting essentially of a device die, an additional package substrate, and combinations thereof. A solder bump bonds the first non-reflowable metal bump to the second non-reflowable metal bump.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: March 11, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chung-Ying Yang, Chao-Wen Shih, Hao-Yi Tsai, Hsien-Wei Chen, Mirng-Ji Lii, Tzuan-Horng Liu
  • Patent number: 8664679
    Abstract: A light emitting device comprises a first layer of an n-type semiconductor material, a second layer of a p-type semiconductor material, and an active layer between the first layer and the second layer. A light coupling structure is disposed adjacent to one of the first layer and the second layer. In some cases, the light coupling structure is disposed adjacent to the first layer. An orifice formed in the light coupling structure extends to the first layer. An electrode formed in the orifice is in electrical communication with the first layer.
    Type: Grant
    Filed: September 29, 2011
    Date of Patent: March 4, 2014
    Assignee: Toshiba Techno Center Inc.
    Inventors: Li Yan, Chao-Kun Lin, Chih-Wei Chuang
  • Patent number: 8653562
    Abstract: An improved structure of the high electron mobility transistor (HEMT) and a fabrication method thereof are disclosed. The improved HEMT structure comprises a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a first etch stop layer, a first n type doped layer formed by AlxGa1-xAs, and a second n type doped layer. The fabrication method comprises steps of: etching a gate, a drain, and a source recess by using a multiple selective etching process. Below the gate, the drain, and the source recess is the Schottky layer. A gate electrode is deposited in the gate recess to form Schottky contact. A drain electrode and a source electrode are deposited to form ohmic contacts in the drain recess and the source recess respectively, and on the second n type doped layer surrounding the drain recess and the source recess respectively.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: February 18, 2014
    Assignee: WIN Semiconductor Corp.
    Inventors: Cheng-Guan Yuan, Shih-Ming Joseph Liu
  • Patent number: 8647031
    Abstract: A semiconductor device includes a metal oxide channel and methods for forming the same. The metal oxide channel includes indium, gallium, and zinc.
    Type: Grant
    Filed: April 25, 2012
    Date of Patent: February 11, 2014
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Randy L. Hoffman, Gregory S. Herman, Peter P. Mardilovich
  • Patent number: 8633541
    Abstract: An integrated circuit contains a voltage protection structure having a diode isolated DENMOS transistor with a guard element proximate to the diode and the DENMOS transistor. The guard element includes an active area coupled to ground. The diode anode is connected to an I/O pad. The diode cathode is connected to the DENMOS drain. The DENMOS source is grounded. A process of forming the integrated circuit is also disclosed.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: January 21, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Farzan Farbiz, Akram A. Salman
  • Patent number: 8623699
    Abstract: A system and method for chip package fabrication is disclosed. The chip package includes a base re-distribution layer having an opening formed therein, an adhesive layer having a window formed therein free of adhesive material, and a die affixed to the base re-distribution layer by way of the adhesive layer, the die being aligned with the window such that only a perimeter of the die contacts the adhesive layer. A shield element is positioned between the base re-distribution layer and adhesive layer that is generally aligned with the opening formed in the base re-distribution layer and the window of the adhesive layer such that only a perimeter of the shield element is attached to the adhesive layer. The shield element is separated from the die by an air gap and is configured to be selectively removable from the adhesive layer so as to expose the front surface of the die.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: January 7, 2014
    Assignee: General Electric Company
    Inventors: Paul Alan McConnelee, Kevin Matthew Durocher, Scott Smith, Laura A. Principe
  • Patent number: 8624318
    Abstract: A semiconductor circuit includes a plurality of semiconductor devices, each including a semiconductor islands having at least one electrical dopant atom and located on an insulator layer. Each semiconductor island is encapsulated by dielectric materials including at least one dielectric material portion. Conductive material portions, at least one of which abut two dielectric material portions that abut two distinct semiconductor islands, are located directly on the at least one dielectric material layer. At least one gate conductor is provided which overlies at least two semiconductor islands. Conduction across a dielectric material portion between a semiconductor island and a conductive material portion is effected by quantum tunneling. The conductive material portions and the at least one gate conductor are employed to form a semiconductor circuit having a low leakage current. A design structure for the semiconductor circuit is also provided.
    Type: Grant
    Filed: April 26, 2012
    Date of Patent: January 7, 2014
    Assignee: International Business Machines Corporation
    Inventors: Zhong-Xiang He, Qizhi Liu
  • Patent number: 8624242
    Abstract: There is offered a semiconductor integrated circuit provided with a function to electrically identify a location where a defect such as chipping of an LSI die or separation of resin is caused. Corresponding to each of the four corners of a semiconductor substrate, each of L-shaped first through fourth peripheral wirings having a first end and a second end is disposed on a periphery of the semiconductor substrate. The first end of each of the first through fourth peripheral wirings is connected with a power supply wiring. Each of first through fourth detection circuits detects breaking of corresponding each of the first through fourth peripheral wirings in response to a voltage at the second end of corresponding each of the first through fourth peripheral wirings, and outputs corresponding each of first through fourth detection signals to corresponding each of output pads.
    Type: Grant
    Filed: December 11, 2012
    Date of Patent: January 7, 2014
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Hiroshi Kojima, Fumio Marutani
  • Patent number: 8624368
    Abstract: A Quad Flat No-Lead (QFN) semiconductor package includes a die pad; I/O connections disposed at the periphery of the die pad; a chip mounted on the die pad; bonding wires; an encapsulant for encapsulating the die pad, the I/O connections, the chip and the bonding wires while exposing the bottom surfaces of the die pad and the I/O connections; a surface layer formed on the bottoms surfaces of the die pad and the I/O connections; a dielectric layer formed on the bottom surfaces of the encapsulant and the surface layer and having openings for exposing the surface layer. The surface layer has good bonding with the dielectric layer that helps to prevent solder material in a reflow process from permeating into the die pad and prevent solder extrusion on the interface of the I/O connections and the dielectric layer, thereby increasing product yield.
    Type: Grant
    Filed: July 26, 2010
    Date of Patent: January 7, 2014
    Assignee: Siliconware Precision Industries Co., Ltd.
    Inventors: Fu-Di Tang, Ching-Chiuan Wei, Yung-Chih Lin
  • Patent number: 8617992
    Abstract: Methods of forming contacts (and optionally, local interconnects) using an ink comprising a silicide-forming metal, electrical devices such as diodes and/or transistors including such contacts and (optional) local interconnects, and methods for forming such devices are disclosed. Electrical devices, such as diodes and transistors may be made using such printed contact and/or local interconnects. A metal ink may be printed for contacts as well as for local interconnects at the same time, or in the alternative, the printed metal can act as a seed for electroless deposition of other metals if different metals are desired for the contact and the interconnect lines. This approach advantageously reduces the number of processing steps and does not necessarily require any etching.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: December 31, 2013
    Assignee: Kovio, Inc.
    Inventors: Aditi Chandra, Arvind Kamath, James Montague Cleeves, Joerg Rockenberger, Mao Takashima, Erik Scher
  • Patent number: 8609496
    Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: December 17, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dongyean Oh, Woon-kyung Lee
  • Patent number: 8604538
    Abstract: A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.
    Type: Grant
    Filed: December 24, 2012
    Date of Patent: December 10, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Hau-Yan Lu, Shih-Chen Wang, Ching-Sung Yang
  • Patent number: 8603845
    Abstract: An array substrate for an organic electroluminescent display device includes a substrate including a display area and a non-display area; a gate line and a data line; a thin film transistor including a semiconductor layer of polycrystalline silicon, a gate insulating layer, a gate electrode, an inter insulating layer, a source electrode, and a drain electrode; auxiliary lines formed of a same material and on a same layer as the data line; a passivation layer of organic insulating material and including a drain contact hole exposing the drain electrode, and an auxiliary line contact hole exposing one of the auxiliary lines; and a first electrode and a line connection pattern on the passivation layer, wherein the first electrode contacts the drain electrode and the line connection pattern contacts the one of the first auxiliary pattern.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: December 10, 2013
    Assignee: LG Display Co., Ltd
    Inventors: Hee-Dong Choi, Seung-Joon Jeon
  • Patent number: 8592944
    Abstract: An electronic device is provided with: a first electronic circuit, integrated in a first die; a second electronic circuit, integrated in a second die; and a galvanic isolator element, designed to insulate galvanically, and to enable transfer of signals between, the first electronic circuit and the second electronic circuit. The galvanic isolator element has: a transformer substrate, distinct from the first die and from the second die; and a galvanic-insulation transformer formed by a first inductive element, integrated in the first die, and by a second inductive element, integrated in the transformer substrate and so arranged as to be magnetically coupled to the first inductive element.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: November 26, 2013
    Assignee: STMicroelectronics S.r.l.
    Inventors: Antonello Santangelo, SantoAlessandro Smerzi
  • Patent number: 8586962
    Abstract: A cross point memory array includes a structure in which holes are formed in an insulating layer and a storage node is formed in each of the holes. The storage node may include a memory resistor and a switching structure. The master for an imprint process used to form the cross-point memory array includes various pattern shapes, and the method of manufacturing the master uses various etching methods.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: November 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-kyu Lee, Du-hyun Lee, Myoung-jae Lee
  • Patent number: 8587090
    Abstract: The invention provides a die seal ring structure. The die seal ring structure includes an inner seal ring portion surrounding an integrated circuit region. An outer seal ring portion is surrounded by a scribe line, surrounding the inner seal ring portion, wherein the outer seal ring portion has an outer top metal layer pattern with a first width extending over the inner seal ring portion and connecting to an inner next-to-top metal layer pattern of the inner seal ring portion. A first redistribution pattern is disposed on the outer top metal layer pattern, having a second width which is narrower than the first width. A second redistribution pattern is disposed on the first redistribution pattern. A redistribution passivation layer covers the second redistribution pattern and the inner seal ring portion, wherein the redistribution passivation layer is separated from the scribe line by a second distance.
    Type: Grant
    Filed: May 22, 2012
    Date of Patent: November 19, 2013
    Assignee: Mediatek Inc.
    Inventors: Tien-Chang Chang, Yu-Hua Huang
  • Patent number: 8569119
    Abstract: A step of forming wiring using first solution ejection means for ejecting a conductive material, a step of forming a resist mask on the wiring using second solution ejection means, and a step of etching the wiring using an atmospheric-pressure plasma device having linear plasma generation means or an atmospheric-pressure plasma device having a plurality of linearly-arranged plasma-generation-means using the resist mask as a mask are included.
    Type: Grant
    Filed: December 8, 2010
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8557713
    Abstract: Semiconductor devices and methods of forming the semiconductor device are provided, the semiconductor devices including a first dielectric layer on a substrate, and a second dielectric layer on the first dielectric layer. The first dielectric layer has a carbon concentration lower than the second dielectric layer.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: October 15, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ha-Jin Lim, Hyung-Suk Jung, Yun-Ki Choi
  • Patent number: 8551850
    Abstract: A method of forming a reversible resistance-switching metal-insulator-metal structure is provided, the method including forming a first non-metallic conducting layer, forming a non-conducting layer above the first non-metallic conducting layer, forming a second non-metallic conducting layer above the non-conducting layer, etching the first non-metallic conducting layer, non-conducting layer and second non-metallic conducting layer to form a pillar, and disposing a carbon material layer about a sidewall of the pillar. Other aspects are also provided.
    Type: Grant
    Filed: December 7, 2009
    Date of Patent: October 8, 2013
    Assignee: SanDisk 3D LLC
    Inventors: Yubao Li, Chu-Chen Fu, Jingyan Zhang
  • Patent number: 8535986
    Abstract: An integrated circuit 15 is placed onto a lead frame 101 having lead fingers 109 of substantially constant thickness along their length. Wires are formed from the lead fingers 109 to corresponding electrical contacts the integrated circuit. Following the wire bonding process, the thickness of the tips of the lead fingers 109 is reduced by a laser process, to form tips of reduced thickness desirable for a subsequent moulding operation. Thus, at the time of the wire bonding the tips of the fingers 109 need not have a gap beneath them, so that more secure wire bonds to the lead fingers 109 can be formed.
    Type: Grant
    Filed: January 13, 2003
    Date of Patent: September 17, 2013
    Assignee: Infineon Technologies AG
    Inventors: Liang Kng Ian Koh, Richard Mangapul Sinaga