Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The remote plasma source may be used to provide a plasma surface treatment or as a source to incorporate dopants into a pre-deposited layer.

Abstract: A static induction transistor is formed on a silicon carbide substrate doped with a first conductivity type. First recessed regions in a top surface of the silicon carbide substrate are filled with epitaxially grown gate regions in situ doped with a second conductivity type. Epitaxially grown channel regions in situ doped with the first conductivity type are positioned between adjacent epitaxial gate regions. Epitaxially grown source regions in situ doped with the first conductivity type are positioned on the epitaxial channel regions. The bottom surface of the silicon carbide substrate includes second recessed regions vertically aligned with the channel regions and silicided to support formation of the drain contact. The top surfaces of the source regions are silicided to support formation of the source contact. A gate lead is epitaxially grown and electrically coupled to the gate regions, with the gate lead silicided to support formation of the gate contact.

Abstract: Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer flux may be provided in the process to mount an IC package to a PCB. The polymer flux may be provided on connectors of the IC package, or provided on PCB contact pad and/or pre-solder of the PCB. When the IC package is mounted onto the PCB, the polymer flux may cover a part of the connector, and may extend to cover a surface of the molding compound on the IC package. The polymer flux may completely cover the connector as well. The polymer flux delivers a fluxing component that facilitates smooth solder joint formation as well as a polymer component that offers added device protection by encapsulating individual connectors. The polymer component may be an epoxy.

Abstract: A semiconductor device includes interlayer dielectrics stacked and spaced apart from each other, a channel layer passing through the interlayer dielectrics, line pattern regions each surrounding a sidewall of the channel layer to be disposed between the interlayer dielectrics, a barrier pattern formed along a surface of each of the line pattern regions and the sidewall of the channel layer, a reaction preventing pattern formed on the barrier pattern along a surface of a first region of each of the line pattern regions, the first region being adjacent to the channel layer, a protection pattern filled in the first region on the reaction preventing pattern, and a first metal layer filled in a second region of each of the line pattern regions.

Abstract: Methods of depositing conformal aluminum nitride films on semiconductor substrates are provided. Disclosed methods involve (a) exposing a substrate to an aluminum-containing precursor, (b) purging the aluminum-containing precursor for a duration insufficient to remove substantially all of the aluminum-containing precursor in gas phase, (c) exposing the substrate to a nitrogen-containing precursor to form aluminum nitride, (d) purging the nitrogen-containing precursor, and (e) repeating (a) through (d). Increased growth rate and 100% step coverage and conformality are attained.

Abstract: In a manufacturing method of a semiconductor device according to an embodiment, a plurality of semiconductor packages each including a semiconductor chip mounted on a wiring board and a sealing resin layer as objects to be processed, and a tray including a plurality of housing parts are prepared. A depressed portion having a non-penetrating shape or a penetrating shape is formed in the housing part. The semiconductor packages are disposed in the plural housing parts respectively. By sputtering a metal material on the semiconductor package housed in the tray, a conductive shield layer is formed.

Abstract: A method comprises depositing a first layer comprising aluminum nitride over a substrate. The method further comprises depositing a second layer comprising aluminum gallium nitride over the first layer. The method also comprises depositing a third layer comprising indium gallium nitride over the second layer. The method additionally comprises removing some of the third layer leaving a first portion of the third layer and a second portion of the third layer. The method further comprises reducing an aluminum content of at least the first layer by drawing aluminum atoms from the first layer into at least the second layer beneath the first portion and the second portion of the third layer. The method also comprises depositing a source contact over the first portion of the third layer and a drain contact over the second portion of the third layer.

Abstract: An organic material layer is lithographically patterned to include a linear array portion of lines and spaces. In one embodiment, the organic material layer can be an organic planarization layer that is patterned employing a photoresist layer, which is consumed during patterning of the organic planarization layer. Volume expansion of the organic planarization layer upon exposure to a halogen-including gas causes portions of the linear array to collapse at random locations. In another embodiment, the height of the photoresist layer is selected such that the linear array portion of the photoresist layer is mechanically unstable and produces random photoresist collapses. The pattern including random modifications due to the collapse of the organic material layer is transferred into an underlying layer to generate an array of conductive material lines with random electrical disruption of shorts or opens. The structure with random shorts can be employed as a physical unclonable function.

Abstract: Integrated circuit devices including fin field-effect transistors (finFETs) and methods of forming the same are provided. The methods may include forming a fin-shaped channel region including germanium on a substrate and forming a source/drain region adjacent the channel region on the substrate. The methods may further include forming a barrier layer contacting sidewalls of the channel region and the source/drain region, and the barrier layer may include SixGe1-x, and x may be in a range of about 0.05 to about 0.2.

Abstract: Forming a resistive memory structure at a temperature well above the operating temperature can reduce the forming voltage and create a defect distribution with higher stability and lower programming voltages. The forming temperature can be up to 200 C above the operating temperature. The memory chip can include an embedded heater in the chip package, allowing for a chip forming process after packaging.

Abstract: The present invention discloses a gate structure, which is applied for an electronic component comprising a substrate and an active region defined thereon, and such the gate structure is disposed in the active region and is a T-shaped gate having a stem with a height of 250 nm. Preferably, the gate structure has a gate length of 60 nm.

Abstract: A method relates to separating a component composite into a plurality of component regions, wherein the component composite is provided having a semiconductor layer sequence comprising a region for generating or for receiving electromagnetic radiation. The component composite is mounted on a rigid subcarrier. The component composite is separated into the plurality of component regions, wherein one semiconductor body is produced from the semiconductor layer sequence for each component region. The component regions are removed from the subcarrier.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to NMOS and PMOS transistor strain.

Abstract: According to an exemplary embodiment, a method of forming a substrate pattern having an isolated region and a dense region is provided. The method includes the following operations: forming a first photoresist layer over the substrate; exposing the first photoresist layer through a first mask corresponding to the isolated region; developing the first photoresist layer to form a first pattern; forming a second photoresist layer over the substrate and the first pattern; exposing the second photoresist layer through a second mask corresponding to the substrate pattern; developing the second photoresist layer to form a second pattern; and etching the first pattern and the substrate to form the substrate pattern in the isolated region and the dense region.

Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of (b) forming, on a back face of a dummy substrate and back faces of a plurality of semiconductor substrates, inorganic films having such thicknesses as to be resistant to a temperature of a thermal oxidizing treatment or a heat treatment and to sufficiently decrease an amount of oxidation or reducing gaseous species to reach the back faces of the dummy substrate and the plurality of semiconductor substrates, (c) disposing the dummy substrate and the plurality of semiconductor substrates in a lamination with surfaces turned in the same direction at an interval from each other, and (d) carrying out a thermal oxidizing treatment or post annealing over the surfaces of the semiconductor substrates in an oxidation gas atmosphere or a reducing gas atmosphere after the steps (b) and (c).

Abstract: A method of forming a wiring may include forming a first wire on a substrate; forming a material layer on the substrate, except on the first wire; forming a surface treatment film on the material layer; and forming a second wire on the first wire. The surface treatment film has physical properties opposite to the first wire. A method of forming a wiring may include forming a first wire on a substrate; forming a material layer on the substrate and the first wire; removing a portion of the material layer from the first wire; forming a surface treatment film on the material layer and the first wire; removing a portion of the surface treatment film from the first wire; and forming a second wire on the first wire. A thickness of the material layer on the substrate is greater than a thickness of the first wire on the substrate.

Abstract: A method of forming a stacked-layer wiring includes forming first wettability variable layer on a substrate using material that changes surface energy by energy application; forming first conductive layer in or on the first wettability variable layer; forming second wettability variable layer on the first wettability variable layer using material that changes surface energy by energy application; forming concave portion to become wiring pattern of second conductive layer to the second wettability variable layer while concurrently forming high surface energy area on surface exposed by forming the concave portion by changing surface energy; forming via hole by exposing a part of the first conductive layer while concurrently forming high surface energy area on surface exposed by forming the via hole by changing surface energy; and applying conductive ink to the high surface energy area to form the second conductive layer and via simultaneously.

Abstract: A method for fabricating a semiconductor structure is disclosed. First, an interposer is disposed on a carrier. The carrier has a base body and a bonding layer bonded to the base body. The interposer has opposite first and second sides and the first side has a plurality of conductive elements. The interposer is disposed on the carrier with the first side bonded to the bonding layer and the conductive elements embedded in the bonding layer. Then, at least a semiconductor element is disposed on the second side of the interposer. As such, the semiconductor element and the interposer form a semiconductor structure. Since the conductive elements are embedded in the bonding layer instead of the base body, the present invention eliminates the need to form concave portions in the base body for receiving the conductive elements. Therefore, the method of the present invention is applicable to interposers of different specifications.

Abstract: The electrostatic discharge protection structure includes an N-well disposed on a substrate, a P-well disposed on the substrate and adjacent to the N-well, a first doped region of N-type conductivity disposed in the N-well, a second doped region of N-type conductivity disposed in the N-well, a third doped region of P-type conductivity disposed in the N-well, a fifth doped region of P-type conductivity disposed in the P-well, a fourth doped region of N-type conductivity disposed between the third doped region and the fifth doped region in the P-well, an anode electrically connected to the first doped region and the second doped region, and a cathode electrically connected to the fourth doped region and the fifth doped region.

Abstract: A method of encapsulating at least one microelectronic device is provided, including encapsulating the device in a cavity hermetically sealed against air, a cap of the cavity including at least one wall permeable to at least one noble gas; injecting the noble gas into the cavity through the wall permeable to the noble gas; hermetically sealing the cavity against air and the injected noble gas; forming the device on at least one first substrate; bonding at least one second substrate to the first substrate, thereby forming the cavity hermetically sealed against air, the wall permeable to the noble gas being formed by part of the second substrate; and forming, between the encapsulating and the injecting, at least one portion of material impermeable to the noble gas such that said portion partially covers the part of the second substrate that forms the wall permeable to the noble gas.