Abstract: A semiconductor structure comprising aluminum oxide. The semiconductor structure comprises a dielectric material overlying a substrate. The aluminum oxide overlies the dielectric material in a first region of the structure. A second region of the structure includes a first titanium nitride portion overlying the dielectric material, magnesium over the first titanium nitride portion, and a second titanium nitride portion over the magnesium. Methods of forming the semiconductor structure including aluminum oxide are also disclosed.

Abstract: A memory cell having a kinked polysilicon layer structure, or a polysilicon layer structure with a top portion being narrower than a bottom portion, may greatly reduce random single bit (RSB) failures and may improve high density plasma (HDP) oxide layer fill-in by reducing defects caused by various impurities and/or a polysilicon layer short path. A kinked polysilicon layer structure may also be applied to floating gate memory cells either at the floating gate structure or the control gate structure.

Abstract: In a method for producing a semiconductor device, Si pillars that include i-layers, N+ regions that serve as lower impurity regions, N+ regions and a P+ region that serve as upper impurity regions, and i-layers are formed by using SiO2 layers as an etching mask. Thus, surrounding gate MOS transistors (SGTs) are produced in which the upper impurity regions and the lower impurity regions respectively function as impurity layers constituting a source or a drain of the SGTs formed in upper portions and lower portions of the Si pillars.

Abstract: A method for manufacturing a field effect transistor of a non-planar type, comprising providing a substrate having an initially planar front main surface, and providing shallow trench isolation structures in the substrate on the front surface, thereby defining a plurality of fin structures in the substrate between the shallow trench isolation structures. Top surfaces of the shallow trench isolation structures and the fin structures abut on a common planar surface, and sidewalls of the fin structures are fully concealed by the shallow trench isolation structures. The method also includes forming a dummy gate structure over a central portion of the plurality of fin structures on the common planar surface, forming dielectric spacer structures around the dummy gate structure, and removing the dummy gate structure, thereby leaving a gate trench defined by the dielectric spacer structures.

Abstract: Narrow word lines are formed in a NAND flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines.

Abstract: Provided are an apparatus for manufacturing an OLED display and a method of manufacturing OLED display. According to another aspect of the present invention, there is provided the method of manufacturing an OLED display which includes placing a substrate having rows and columns of pixels through on a stage, ejecting organic light-emitting ink to the pixels through on the substrate by using a print head placed above the stage, and sequentially covering pixels through coated with the organic light-emitting ink with a cover plate placed above the stage.

Abstract: Circuit fabrication methods are provided which include, for example: providing the circuit structure with at least one gate structure extending over a first region and a second region of a substrate structure, the at least one gate structure including a capping layer; and modifying an etch property of at least a portion of the capping layer of the at least one gate structure, where the modified etch property inhibits etching of the at least one gate structure during a first etch process facilitating fabrication of at least one first transistor in the first region and inhibits etching of the at least one gate structure during a second etch process facilitating fabrication of at least one second transistor in the second region.

Abstract: In a wafer processing method, the back side of the wafer is ground to reduce the thickness of the wafer to a predetermined thickness. A modified layer is formed by applying a laser beam to the wafer from the back side of the wafer along each division line with the focal point of the laser beam set inside the wafer. The wafer is mounted on a reinforcing sheet having an insulating function on the back side of the wafer and a dicing tape is attached to the reinforcing sheet. The peripheral portion of the dicing tape is supported by an annular frame. The wafer is heated, which also heats the reinforcing sheet, thereby hardening the reinforcing sheet. An external force is applied to the wafer to divide the wafer into individual devices along each division line and to also break the reinforcing sheet along the individual devices.

Abstract: Provided is a manufacturing method of a semiconductor device including providing a substrate including a first region and a second region, forming active fins in the first region and the second region, forming gate electrodes which intersect the active fins and have surfaces facing side surfaces of the active fins, forming an off-set zero (OZ) insulation layer covering the active fins, forming a first residual etch stop layer and a first hard mask pattern which cover the first region, injecting first impurities into the active fins of the second region, removing the first hard mask pattern and the first residual etch stop layer, forming second residual etch stop layer and a second hard mask pattern which cover the second region, injecting a second impurities into the active fins of the first region, and removing the second residual etch stop layer and the second hard mask pattern.

Abstract: A wafer is divided into a plurality of individual devices along a plurality of crossing division lines formed on the front side of the wafer. The wafer has a substrate, a functional layer formed on the front side of the substrate, and an SiO2 film formed on the front side of the functional layer. The individual devices are formed from the functional layer and partitioned by the division lines. The functional layer is removed by applying a laser beam to the wafer along each division line to thereby remove the functional layer along each division line. The laser beam has an absorption wavelength to the SiO2 film with high absorptivity due to the stretching vibration of an O—H bond or a C—H bond remaining in the SiO2 film. The wafer is then divided into the individual devices.

Abstract: This document relates to a method of forming low-resistance metal gate and data wirings and a method of manufacturing a thin film transistor using the same. The method of the wiring includes depositing a metal layer on a base layer; exposing a portion of the base layer by removing a portion of the metal layer; forming grooves in the base layer; forming a seed layer in the grooves of the base layer; and forming a wire consisting of the seed layer and a plated layer by plating a plating material on the seed layer formed in the grooves of the base layer.

Abstract: Methods for fabricating graphene nanoelectronic devices with semiconductor compatible processes, which allow wafer scale fabrication of graphene nanoelectronic devices, is provided. One method includes the steps of preparing a dispersion of functionalized graphene in a solvent; and applying a coating of said dispersion onto a substrate and evaporating the solvent to form a layer of functionalized graphene; and defunctionalizing the graphene to form a graphene layer on the substrate.

Abstract: Embodiments of the present disclosure provide a method for controlling moisture from substrate being processed. Particularly, embodiments of the present disclosure provide methods for removing moisture from polymer materials adjacent bond pad areas. One embodiment of the present includes providing a moisture sensitive precursor and forming a compound from a reaction between the moisture to be controlled and the moisture sensitive precursor.

Abstract: The invention relates to a process for thinning the active silicon layer of a substrate, which comprises an insulator layer between the active layer and a support, this process comprising one step of sacrificial thinning of active layer by formation of a sacrificial oxide layer by sacrificial thermal oxidation and deoxidation of the sacrificial oxide layer. The process is noteworthy in that it comprises: a step of forming a complementary oxide layer on the active layer, using an oxidizing plasma, this layer having a thickness profile complementary to that of oxide layer, so that the sum of the thicknesses of the oxide layer and of the sacrificial silicon oxide layer are constant over the surface of the treated substrate, a step of deoxidation of this oxide layer, so as to thin active layer by a uniform thickness.

Abstract: A device wafer has a plurality of devices individually formed in a plurality of separate regions on the front side of the wafer, the separate regions being defined by a plurality of crossing division lines. The wafer is processed by imaging the front side of the wafer to detect and store a target pattern, holding the front side of the wafer and grinding the back side of the wafer to thereby reduce the thickness to a predetermined thickness, imaging the front side of the wafer and next positioning the wafer with respect to a ring frame according to the target pattern stored so that the wafer is oriented to a predetermined direction, and attaching an adhesive tape to the back side of the wafer to thereby mount the wafer through the adhesive tape to the ring frame.

Abstract: A TSV exposing process is provided, including: performing a mechanical grinding process on the substrate back surface of a substrate with a TSV conductive column, a liner between the substrate and the TSV conductive column; performing a first and a second chemical mechanical polishing process on the grinded substrate back surface; then performing an etching on the substrate back surface, and making the TSV backside reveal more than 10 ?m.

Abstract: A method of producing at least one optoelectronic semiconductor chip includes providing at least one optoelectronic structure, including a growth support and a semiconductor layer sequence with an active region, the semiconductor layer sequence being deposited epitaxially on the growth support, providing a carrier, applying the at least one optoelectronic structure onto the carrier with its side remote from the growth support, coating the at least one optoelectronic structure with a protective material, the protective material covering the outer face, remote from the carrier, of the growth support and side faces of the growth support and of the semiconductor layer sequence, and detaching the growth support from the semiconductor layer sequence of the at least one optoelectronic structure.

Abstract: A method (50) is provided for processing a graded-density AR silicon surface (14) to provide effective surface passivation. The method (50) includes positioning a substrate or wafer (12) with a silicon surface (14) in a reaction or processing chamber (42). The silicon surface (14) has been processed (52) to be an AR surface with a density gradient or region of black silicon. The method (50) continues with heating (54) the chamber (42) to a high temperature for both doping and surface passivation. The method (50) includes forming (58), with a dopant-containing precursor in contact with the silicon surface (14) of the substrate (12), an emitter junction (16) proximate to the silicon surface (14) by doping the substrate (12). The method (50) further includes, while the chamber is maintained at the high or raised temperature, forming (62) a passivation layer (19) on the graded-density silicon anti-reflection surface (14).

Abstract: It is advantageous to create texture at the surface of a photovoltaic cell to reduce reflection and increase travel length of light within the cell. A method is disclosed to create texture at the surface of a silicon body by reacting a silicide-forming metal at the surface, where the silicide-silicon interface is non-planar, then stripping the silicide, leaving behind a textured surface. Depending on the metal and the conditions of silicide formation, the resulting surface may be faceted. The peak-to-valley height of this texturing will generally be between about 300 and about 5000 angstroms, which is well-suited for use in photovoltaic cells comprising a thin silicon lamina.

Abstract: A wafer processing method, by which a device wafer may be aligned and bonded to a carrier wafer to perform a back grinding process for the device wafer and may be separated from the carrier wafer after performing the back grinding process, and a method of manufacturing a semiconductor device by using the wafer processing method are provided. The wafer processing method includes: disposing a first magnetic material on a front side of a wafer and disposing a second magnetic material on a carrier wafer, wherein a surface of the first magnetic material and a surface of the second magnetic material, which face each other, have opposite polarities; aligning and bonding the wafer to the carrier wafer by magnetic attraction between the first magnetic material and the second magnetic material; grinding a back side of the wafer to make the wafer thin; and separating the wafer from the carrier wafer.