Patents Examined by Thao P. Le
  • Patent number: 10734505
    Abstract: A structure and method of forming a lateral bipolar junction transistor (LBJT) that includes: a first base layer, a second base layer over the first base layer, and an emitter region and collector region present on opposing sides of the first base layer, where the first base layer has a wider-band gap than the second base layer, and where the first base layer includes a III-V semiconductor material.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: August 4, 2020
    Assignee: International Business Machines Corporation
    Inventors: Pouya Hashemi, Bahman Hekmatshoartabari, Alexander Reznicek, Karthik Balakrishnan, Jeng-Bang Yau
  • Patent number: 10734406
    Abstract: According to one embodiment, a semiconductor memory device includes first conductive films, a second conductive film, a first pillar including a first semiconductor film and a first insulator, a second semiconductor film, and a second pillar including a second insulator and a third conductive film. The first conductive films are stacked with respective insulator layers interposed therebetween. The second conductive film is provided above the first conductive films with an insulator layer interposed therebetween. The first semiconductor film penetrate the first conductive films in a stacking direction of the first conductive films. The first insulator is provided on a side surface of the first semiconductor film.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: August 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroyuki Yamasaki, Hideaki Harakawa
  • Patent number: 10720487
    Abstract: A structure and a formation method of a semiconductor device are provided. The method includes forming an etch stop layer over a semiconductor substrate and forming a magnetic element over the etch stop layer. The method also includes forming an isolation element extending across the magnetic element. The isolation element partially covers the top surface of the magnetic element and partially covers sidewall surfaces of the magnetic element. The method further includes forming a conductive line over the isolation element. In addition, the method includes forming a dielectric layer over the conductive line, the isolation element, and the magnetic element.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: July 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Chi-Cheng Chen, Hon-Lin Huang, Wei-Li Huang, Chun-Yi Wu, Chen-Shien Chen
  • Patent number: 10714434
    Abstract: An embedded magnetic inductor coil is at least partially exposed in a recess that seats an embedded multi-chip interconnect bridge die on the coil. The embedded multi-chip interconnect bridge die provides a communications bridge between a dominant semiconductive device and a first semiconductive device.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: July 14, 2020
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Kristof Darmawikarta, Aleksandar Aleksov
  • Patent number: 10707309
    Abstract: To provide a new GaN laminate obtained b growing a GaN layer on a GaN substrate by HVPE, including: a GaN substrate containing GaN single crystal and having a low index crystal plane as c-plane closest to a main surface; and a GaN layer epitaxially grown on the main surface of the GaN substrate wherein a surface of the GaN layer has a macro step-macro terrace structure in which a macro step and a macro terrace are alternately arranged, one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to m-axis direction, and a terrace are alternately arranged, and the other one of the macro step and the macro terrace has a step-terrace structure in which a step having a height of equal to or more than a plurality of molecular layers of GaN and extending in a direction orthogonal to a-axis direction, and a terrace are alternately arranged.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: July 7, 2020
    Assignees: SCIOCS COMPANY LIMITED, SUMITOMO CHEMICAL COMPANY, LIMITED
    Inventor: Hajime Fujikura
  • Patent number: 10699976
    Abstract: A semiconductor module includes a semiconductor die, a mold compound encasing the semiconductor die, a plurality of terminals electrically connected to the semiconductor die and protruding out of the mold compound, wherein a first one of the terminals has a constricted region covered by the mold compound, wherein the mold compound has a recess or an opening near the constricted region of the first terminal, and a coreless magnetic field sensor disposed in the recess or the opening of the mold compound and isolated from the first terminal by the mold compound. The coreless magnetic sensor is configured to generate a signal in response to a magnetic field produced by current flowing in the constricted region of the first terminal. The magnitude of the signal is proportional to the amount of current flowing in the constricted region of the first terminal. A method of manufacturing the module also is described.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: June 30, 2020
    Assignee: Infineon Technologies AG
    Inventors: Juergen Hoegerl, Leo Aichriedler, Christian Schweikert, Gerald Wriessnegger
  • Patent number: 10692867
    Abstract: The present disclosure describes a fin-like field-effect transistor (FinFET). The device includes one or more fin structures over a substrate, each with source/drain (S/D) features and a high-k/metal gate (HK/MG). A first HK/MG in a first gate region wraps over an upper portion of a first fin structure, the first fin structure including an epitaxial silicon (Si) layer as its upper portion and an epitaxial growth silicon germanium (SiGe), with a silicon germanium oxide (SiGeO) feature at its outer layer, as its middle portion, and the substrate as its bottom portion. A second HK/MG in a second gate region, wraps over an upper portion of a second fin structure, the second fin structure including an epitaxial SiGe layer as its upper portion, an epitaxial Si layer as it upper middle portion, an epitaxial SiGe layer as its lower middle portion, and the substrate as its bottom portion.
    Type: Grant
    Filed: December 12, 2018
    Date of Patent: June 23, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Cheng Ching, Ka-Hing Fung, Chih-Sheng Chang, Zhiqiang Wu
  • Patent number: 10686096
    Abstract: A lead frame includes a main plate and a side plate. The main plate has a support portion and a projecting portion. The support portion has two opposite first sides and a support face located between the first sides. The projecting portion projects upward from one of the first sides in a direction opposite to the support face. The side plate is disposed separately from the one of the first sides of the support portion and is spaced apart from the projecting portion.
    Type: Grant
    Filed: November 12, 2018
    Date of Patent: June 16, 2020
    Assignees: LITE-ON OPTO TECHNOLOGY (CHANGZHOU) CO., LTD., LITE-ON TECHNOLOGY CORP.
    Inventors: Tsan-Yu Ho, Chen-Hsiu Lin, Meng-Sung Chou
  • Patent number: 10680069
    Abstract: In accordance with an embodiment, a circuit includes a first gallium nitride (GaN) transistor comprising a drain coupled to a drain node, a source coupled to a source node, and a gate coupled to a gate node; and a second GaN transistor comprising a drain coupled to the drain node, a source coupled to a first power source node configured to be coupled to a first capacitor.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: June 9, 2020
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Oliver Haeberlen, Gerald Deboy
  • Patent number: 10672834
    Abstract: According to the embodiment, a semiconductor memory device includes a first conductive layer, a second conductive layer, a first memory cell, a second memory cell, a third conductive layer, a first contact, a intermediate memory cell, a fourth conductive layer, a third memory cell, a fifth conductive layer, and a second contact. The third conductive layer is separated from the first conductive layer and the second conductive layer in a third direction crossing a first direction and crossing a second direction and extends in the second direction. The fifth conductive layer is separated from the second conductive layer in the third direction and extends in the second direction. A first length of the second conductive layer along the second direction is shorter than a second length of the fifth conductive layer along the second direction.
    Type: Grant
    Filed: February 22, 2019
    Date of Patent: June 2, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Yusuke Kobayashi, Yoshihisa Iwata, Takeshi Sugimoto
  • Patent number: 10672806
    Abstract: FET IC structures that enable formation of high-Q inductors in a “flipped” SOI IC structure made using a back-side access process, such as an single layer transfer (SLT) process. Essentially, the interconnect layer superstructure of an IC is split into two parts, a “lower” superstructure and an “upper” superstructure. In various embodiments, one or more low-resistance interconnect layers are fabricated within an upper superstructure formed after the application of a back-side access process, allowing fabrication of inductors in one or more low-resistance interconnect layer. A significant advantage of such IC structures is that the low-resistance interconnect layer or layers are relocated from being near the handle wafer of a conventional SLT IC to being spaced away from the handle wafer by intervening structures. Fabricating inductors in such spaced low-resistance interconnect layer or layers reduces electromagnetic coupling with the handle wafer and thus increases the Q factor of the inductors.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: June 2, 2020
    Assignee: pSemi Corporation
    Inventors: Abhijeet Paul, Hiroshi Yamada, Alain Duvallet
  • Patent number: 10658261
    Abstract: A semiconductor device includes a first semiconductor element having an upper electrode and a lower electrode, a first upper heat sink connected to the upper electrode, and a first lower heat sink connected to the lower electrode. The first lower heat sink is opposed to the first upper heat sink such that the first semiconductor element is sandwiched between the upper and lower heat sinks. One of the first upper heat sink and the first lower heat sink is a laminated substrate having an insulator substrate (such as a ceramic substrate) and conductor layers disposed on opposite surfaces of the insulator substrate, and the other of the first upper heat sink and the first lower heat sink is a conductor plate that is a conductor having higher thermal conductivity than the insulator substrate.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 19, 2020
    Assignee: Denso Corporation
    Inventor: Takanori Kawashima
  • Patent number: 10658586
    Abstract: Embodiments of the present invention include RRAM devices and their methods of fabrication. In an embodiment, a resistive random access memory (RRAM) cell includes a conductive interconnect disposed in a dielectric layer above a substrate. An RRAM device is coupled to the conductive interconnect. An RRAM memory includes a bottom electrode disposed above the conductive interconnect and on a portion of the dielectric layer. A conductive layer is formed on the bottom electrode layer. The conductive layer is separate and distinct from the bottom electrode layer. The conductive layer further includes a material that is different from the bottom electrode layer. A switching layer is formed on the conductive layer. An oxygen exchange layer is formed on the switching layer and a top electrode is formed on the oxygen exchange layer.
    Type: Grant
    Filed: July 2, 2016
    Date of Patent: May 19, 2020
    Assignee: Intel Corporation
    Inventors: James S. Clarke, Ravi Pillarisetty, Uday Shah, Tejaswi K. Indukuri, Niloy Mukherjee, Elijah V. Karpov, Prashant Majhi
  • Patent number: 10658387
    Abstract: A method for forming a semiconductor structure includes forming a strained silicon germanium layer on top of a substrate. At least one patterned hard mask layer is formed on and in contact with at least a first portion of the strained silicon germanium layer. At least a first exposed portion and a second exposed portion of the strained silicon germanium layer are oxidized. The oxidizing process forms a first oxide region and a second oxide region within the first and second exposed portions, respectively, of the strained silicon germanium.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: May 19, 2020
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Juntao Li, Zuoguang Liu, Xin Miao
  • Patent number: 10658466
    Abstract: A semiconductor element includes: a semiconductor substrate of a first conduction type; a silicon carbide semiconductor layer of the first conduction type disposed above a principal surface of the semiconductor substrate; a terminal edge region of a second conduction type disposed in the silicon carbide semiconductor layer; an insulating film; a first electrode disposed on the silicon carbide semiconductor layer; and a seal ring surrounding the first electrode. The terminal edge region is disposed to surround part of a surface of the silicon carbide semiconductor layer when viewed in a normal direction of the principal surface of the semiconductor substrate. The terminal edge region includes a guard ring region of the second conduction type, and a terminal edge injection region of the second conduction type. The seal ring is formed on the terminal edge injection region through an opening disposed on the insulating film.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: May 19, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventor: Masao Uchida
  • Patent number: 10651377
    Abstract: The present disclosure provides a storage element, a storage device, a method for manufacturing the same and a driving method. The method for manufacturing the storage element includes: providing a substrate; preparing a thin film transistor on the substrate; and preparing a storage functional pattern by using a phase change material, in which the storage functional pattern is connected to a drain electrode of the thin film transistor.
    Type: Grant
    Filed: August 3, 2018
    Date of Patent: May 12, 2020
    Assignees: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Ruiyong Wang, Lianjie Qu, Ruizhi Yang, Yang You
  • Patent number: 10651279
    Abstract: The present disclosure relates to a semiconductor device and a manufacturing method, and more particularly to a semiconductor interconnect structure incorporating a graphed barrier layer. The present disclosure provides a method of forming a graphed barrier layer by thermally annealing amorphous carbon layers on metal catalyst surfaces. The thickness of the graphed barrier layers can be selected by varying the thickness of the amorphous carbon layer.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: May 12, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shin-Yi Yang, Ching-Fu Yeh, Ming-Han Lee, Shau-Lin Shue
  • Patent number: 10651290
    Abstract: A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a contact etch stop layer (CESL) on the gate structure, forming an interlayer dielectric (ILD) layer around the gate structure, performing a curing process so that an oxygen concentration of the CESL is different from the oxygen concentration of the ILD layer, and then performing a replacement metal gate process (RMG) process to transform the gate structure into a metal gate.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: May 12, 2020
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
  • Patent number: 10643963
    Abstract: A semiconductor structure and its fabrication method are provided. The fabrication method includes: providing a base substrate including a wiring region and an isolation region. A patterned layer is formed on the isolation region of the base substrate and the patterned layer exposes the wiring region of the base substrate. After forming the patterned layer, a redistribution layer is formed on the wiring region of the based substrate exposed by the patterned layer. A protective layer is formed on the redistribution layer, and after forming the protective layer, the patterned layer is removed.
    Type: Grant
    Filed: June 20, 2018
    Date of Patent: May 5, 2020
    Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) Corporation
    Inventor: Feng Ping Cai
  • Patent number: 10636784
    Abstract: A display device includes a substrate; a plurality of pixels on the substrate; a drive circuit on the substrate; a first terminal and a second terminal connected to the pixels or the drive circuit and arranged on the substrate; a first wiring having a first end part connected with the first terminal, and a second end part located on an end part of the substrate; a second wiring having a third end part connected with the second terminal, and a fourth end part located on an end part of the substrate; a first current blocking unit blocking a current flowing in a direction from the second end part to the first end part of the first wiring; and a second current blocking unit blocking a current flowing in a direction from the fourth end part to the third end part of the second wiring.
    Type: Grant
    Filed: November 27, 2018
    Date of Patent: April 28, 2020
    Assignee: Japan Display Inc.
    Inventor: Naohisa Andou