Patents Examined by Thao P. Le
  • Patent number: 12009278
    Abstract: Provided is a package structure including a substrate, a stiffener ring, an eccentric die, a lid layer, and a buffer layer. The stiffener ring is disposed on the substrate. The stiffener ring has an inner perimeter to enclose an accommodation area. The eccentric die is disposed within the accommodation area on the substrate. The eccentric die is offset from a center of the accommodation area to close to a first side of the stiffener ring. The lid layer is disposed on the stiffener ring and overlays the eccentric die. The buffer layer is embedded in the lid layer between the first side of the stiffener ring and the eccentric die. The buffer layer has a thickness less than a thickness of the lid layer.
    Type: Grant
    Filed: November 10, 2022
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Shen Yeh, Yu-Sheng Lin, Ming-Chih Yew, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11990451
    Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and filling an insulating dielectric in a gap between a sidewall of the groove and the semiconductor die stack to form an insulating dielectric layer covering an upper surface of the semiconductor die stack to seal up the semiconductor die stack so as to form the semiconductor package structure.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: May 21, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jie Liu, Zhan Ying
  • Patent number: 11990461
    Abstract: An integrated circuit package including a substrate configured to receive one or more high-bandwidth memory (HBM) stacks on the substrate, an interposer positioned on the substrate and configured to receive a logic die on the interposer, a plurality of interposer channels formed in the interposer and connecting the logic die to the one or more HBM stacks, and a plurality of substrate traces formed in the substrate and configured to interface the plurality of interposer channels to the one or more HBM stacks.
    Type: Grant
    Filed: October 20, 2022
    Date of Patent: May 21, 2024
    Assignee: Google LLC
    Inventors: Nam Hoon Kim, Woon-Seong Kwon, Teckgyu Kang, Yujeong Shim
  • Patent number: 11984429
    Abstract: Leadless power amplifier (PA) packages having topside termination interposer (TTI) arrangements, and associated fabrication methods, are disclosed. Embodiments of the leadless PA package include a base flange, a first set of interposer mount pads, a first RF power die, a package body. The first RF power die is attached to a die mount surface of the base flange and electrically interconnected with the first set of interposer mount pads. The TTI arrangement is electrically coupled to the first set of interposer mount pads and projects therefrom in the package height direction. The package body encloses the first RF power die and having a package topside surface opposite the lower flange surface. Topside input/output terminals of the PA package are accessible from the package topside surface and are electrically interconnected with the first RF power die through the TTI arrangement and the first set of interposer mount pads.
    Type: Grant
    Filed: September 30, 2021
    Date of Patent: May 14, 2024
    Assignee: NXP USA, Inc.
    Inventors: Yun Wei, Scott Duncan Marshall, Lakshminarayan Viswanathan, Taek Kyu Kim, Ricardo Uscola, Fernando A. Santos
  • Patent number: 11978723
    Abstract: A 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. The top die layer and/or the bottom die layer each includes devices such as computing units, Analog-to-Digital converters, analog circuits, RF circuits, logic circuits, sensors, Input/Output devices, and/or memory devices. The devices on the first and the second die layers are laterally surrounded by, or adjacent, vertical interconnect structures (VIS).
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tzu-Hsien Yang, Hiroki Noguchi, Hidehiro Fujiwara, Yih Wang
  • Patent number: 11973058
    Abstract: A semiconductor die package that has a substrate with one or more substrate layers with one or more substrate connections. A substrate layer can include one or more redistribution layers (RDLs). One or more dies (e.g., multiple dies) are disposed on a top substrate layer. The dies have one or more die external connections. Some of the die external connections are electrically connected to one or more substrate connections. One or more metallic dam stiffeners form into a dam enclosure that is disposed on and physically connected to the top substrate layer. The dam enclosure encloses one or more of the dies. The metallic dam enclosure has one or more electrically connected regions where the metallic dam enclosure is electrically connected to one or more of the substrate horizontal connections and one or more electrically insulated regions where the metallic dam enclosure is electrically insulated from one or more of the substrate horizontal connections and the substrate via connections.
    Type: Grant
    Filed: November 25, 2021
    Date of Patent: April 30, 2024
    Assignee: International Business Machines Corporation
    Inventors: Katsuyuki Sakuma, Mukta Ghate Farooq, John Knickerbocker
  • Patent number: 11973001
    Abstract: Semiconductor devices and methods of manufacture which utilize lids in order to constrain thermal expansion during annealing are presented. In some embodiments lids are placed and attached on encapsulant and, in some embodiments, over first semiconductor dies. As such, when heat is applied, and the encapsulant attempts to expand, the lid will work to constrain the expansion, reducing the amount of stress that would otherwise accumulate within the encapsulant.
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Shen Yeh, Chin-Hua Wang, Chia-Kuei Hsu, Po-Yao Lin, Shin-Puu Jeng
  • Patent number: 11973005
    Abstract: A method includes bonding a first package and a second package over a package component, adhering a first Thermal Interface Material (TIM) and a second TIM over the first package and the second package, respectively, dispensing an adhesive feature on the package component, and placing a heat sink over and contacting the adhesive feature. The heat sink includes a portion over the first TIM and the second TIM. The adhesive feature is then cured.
    Type: Grant
    Filed: August 3, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Hsun Wang, Ping-Yin Hsieh, Pu Wang, Li-Hui Cheng, Szu-Wei Lu
  • Patent number: 11967581
    Abstract: A package structure includes a lower substrate, substrate connection terminals on the lower substrate, a semiconductor package on the substrate connection terminals, the semiconductor package including a package substrate and a first encapsulant covering the package substrate, first underfills between the lower substrate and the semiconductor package, the first underfills covering corner portions of the semiconductor package, as viewed in a plan view, and covering at least one of the substrate connection terminals, and a second underfill between the lower substrate and the semiconductor package, the second underfill covering a side surface of the semiconductor package in a plan view.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: April 23, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jinwoo Park, Unbyoung Kang, Jongho Lee, Teakhoon Lee
  • Patent number: 11967583
    Abstract: A semiconductor device, the device comprising: a first substrate; a first metal layer disposed over said substrate; a second metal layer disposed over said first metal layer; a first level comprising a plurality of transistors, said first level disposed over said second metal layer, wherein said plurality of transistors comprise single crystal silicon; a third metal layer disposed over said first level; a fourth metal layer disposed over said third metal layer, wherein said fourth metal layer is aligned to said first metal layer with a less than 200 nm alignment error; and a via disposed through said first level, wherein said via has a diameter of less than 450 nm, wherein said fourth metal layer provides a global power distribution, and wherein said via is directly connected to at least one of said plurality of transistors.
    Type: Grant
    Filed: June 27, 2023
    Date of Patent: April 23, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11961854
    Abstract: A semiconductor device, including a dielectric layer and a semiconductor substrate, is provided. The dielectric layer has a convexity or a concavity. The semiconductor substrate includes a first type semiconductor layer and a second type semiconductor layer sequentially stacked on the dielectric layer. The first type semiconductor layer is disposed on the convexity or the concavity. A top surface and a bottom surface of the first type semiconductor layer are protruded according to the convexity or recessed according to the concavity. A bottom surface of the second type semiconductor layer is protruded according to the convexity or recessed according to the concavity.
    Type: Grant
    Filed: March 17, 2021
    Date of Patent: April 16, 2024
    Inventor: Sywe Neng Lee
  • Patent number: 11961827
    Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where processing of the device includes use of a carrier wafer.
    Type: Grant
    Filed: December 23, 2023
    Date of Patent: April 16, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist
  • Patent number: 11955464
    Abstract: A semiconductor package including a first semiconductor chip, a second semiconductor chip disposed on the first semiconductor chip, and a third semiconductor chip disposed on the second semiconductor chip. A first pad is disposed on a top surface of the second semiconductor chip, and includes a first portion and a second portion protruding in a vertical direction from the first portion. A width of the first portion in a first horizontal direction is greater than a width of the second portion in the first horizontal direction. A second pad is disposed on a bottom surface of the third semiconductor chip facing the top surface of the second semiconductor chip, and a solder ball is disposed as surrounding a sidewall of the second portion of the first pad between the first pad and the second pad.
    Type: Grant
    Filed: January 4, 2023
    Date of Patent: April 9, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Myung Kee Chung, Hyun Soo Chung, Tae Won Yoo
  • Patent number: 11948878
    Abstract: A semiconductor device substrate assembly may include a first substrate, comprising: a first insulator plate; and a first patterned metal layer, disposed on the first insulator plate, wherein the first insulator plate comprises a first material and a first thickness. The assembly may include a second substrate, comprising: a second insulator plate; and a second patterned metal layer, disposed on the second insulator plate, wherein the second insulator plate comprises the first material and the first thickness. The assembly may also include a third substrate, disposed between the first substrate and the second substrate, comprising: a third insulator plate; and a third patterned metal layer, disposed on the third insulator plate, wherein the third insulator plate comprises a second material and a second thickness, wherein at least one of the second material and the second thickness differs from the first material and the first thickness, respectively.
    Type: Grant
    Filed: September 8, 2022
    Date of Patent: April 2, 2024
    Assignee: LITTELFUSE, INC.
    Inventor: Stefan Steinhoff
  • Patent number: 11948896
    Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
  • Patent number: 11948920
    Abstract: Provided are a semiconductor device and a method for manufacturing the same, and a semiconductor package. The semiconductor device includes a die stack and a cap substrate. The die stack includes a first die, second dies stacked on the first die, and a third die stacked on the second dies. The first die includes first through semiconductor vias. Each of the second dies include second through semiconductor vias. The third die includes third through semiconductor vias. The cap substrate is disposed on the third die of the die stack. A sum of a thickness of the third die and a thickness of the cap substrate ranges from about 50 ?m to about 80 ?m.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: I-Chun Hsu, Yan-Zuo Tsai, Chia-Yin Chen, Yang-Chih Hsueh, Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 11942335
    Abstract: A method of manufacturing a module is disclosed. In one example, the method comprises providing at least one solder body with a base portion and an elevated edge extending along at least part of a circumference of the base portion. At least one carrier, on which at least one electronic component is mounted, is placed in the at least one solder body so that the at least one carrier is positioned on the base portion and is spatially confined by the elevated edge.
    Type: Grant
    Filed: November 17, 2022
    Date of Patent: March 26, 2024
    Assignee: Infineon Technologies AG
    Inventors: Achim Muecke, Arthur Unrau
  • Patent number: 11942459
    Abstract: A semiconductor device package includes a first substrate having an electrical circuit, semiconductor dies stacked one on top of the other, and bond wires electrically connected one to another. The bond wires electrically couple the semiconductor dies to one another and to the electrical circuit. There is a first bond wire having a first portion connected to a first semiconductor die, a second portion connected to a second semiconductor die, and an intermediate portion between the first portion and second portion. The semiconductor device package further includes a molding compound encapsulating the semiconductor dies, and the first and second portions of the first bond wire. The intermediate portion of the first bond wire is exposed along a top planar surface of the molding compound. The semiconductor device package may be used for coupling one or more other semiconductor device packages thereto via the exposed intermediate portion.
    Type: Grant
    Filed: February 14, 2022
    Date of Patent: March 26, 2024
    Assignee: Western Digital Technologies, Inc.
    Inventors: Hua Tan, Hope Chiu, Weiting Jiang, Elley Zhang, Cong Zhang, Simon Dong, Jerry Tang, Rosy Zhao
  • Patent number: 11929350
    Abstract: Embodiments provide a method for packaging a semiconductor, a semiconductor package structure, and a package. The packaging method includes: providing a substrate wafer having a first surface and a second surface arranged opposite to each other, the first surface having a plurality of grooves, a plurality of electrically conductive pillars being provided at a bottom of the groove, and the electrically conductive pillar penetrating through the bottom of the groove to the second surface; providing a plurality of semiconductor die stacks; placing the semiconductor die stack in the groove; and filling an insulating dielectric in a gap between a sidewall of the groove and the semiconductor die stack to form an insulating dielectric layer covering an upper surface of the semiconductor die stack to seal up the semiconductor die stack so as to form the semiconductor package structure.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: March 12, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Jie Liu, Zhan Ying
  • Patent number: 11916045
    Abstract: A semiconductor device, the device including: a first substrate; a first metal layer disposed over the first substrate; a second metal layer disposed over the first metal layer; a first level including a plurality of transistors, the first level disposed over the second metal layer, where the plurality of transistors each include single crystal silicon; a third metal layer disposed over the first level; a fourth metal layer disposed over the third metal layer, where the fourth metal layer is aligned to the first metal layer with a less than 200 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm, where the fourth metal layer provides a global power distribution, and where the device includes at least one power supply circuit.
    Type: Grant
    Filed: August 21, 2023
    Date of Patent: February 27, 2024
    Assignee: Monolithic 3D Inc.
    Inventors: Zvi Or-Bach, Brian Cronquist