Patents Examined by Thao P. Le
  • Patent number: 11404379
    Abstract: A method for fabricating a bridge chip assembly for interconnecting two or more IC dies is provided. Each of the IC dies has a first region including first connections having a first pitch and has a second region including second connections or connection pads having a second pitch, the first pitch being greater than the second pitch. The method includes: attaching a non-conductive underfill film on an upper surface of at least the second region of each of the IC dies; bonding the second connections/connection pads of a first IC die to corresponding first connection pads/connections of a bridge chip; and bonding the second connections/connection pads of a second IC die to the bridge chip. The bridge chip assembly includes the bridge chip bonded with the first and second IC dies, and the non-conductive underfill film disposed between the bridge chip and the IC dies.
    Type: Grant
    Filed: November 17, 2020
    Date of Patent: August 2, 2022
    Assignee: International Business Machines Corporation
    Inventors: Mukta Ghate Farooq, Katsuyuki Sakuma
  • Patent number: 11398429
    Abstract: An electronic package is provided, which is disposed with a second electronic component and a third electronic component on a first electronic component as a carrier structure, such that there is no need to match a layout size of the conventional package substrate. Therefore, the first electronic component can be designed as a System on a Chip (SoC) with a smaller size to improve the process yield.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: July 26, 2022
    Assignee: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Cheng Kai Chang, Chang-Fu Lin, Don-Son Jiang
  • Patent number: 11380669
    Abstract: A method of forming a microelectronic device comprises forming a source material around substantially an entire periphery of a base material, and removing the source material from lateral sides of the base material while maintaining the source material over an upper surface and a lower surface of the base material. Related methods and base structures for microelectronic devices are also described.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: July 5, 2022
    Assignee: Micron Technology, Inc.
    Inventor: Kunal R. Parekh
  • Patent number: 11373991
    Abstract: Methods of manufacturing light-emitting devices are described herein. A method includes obtaining a packaging substrate. The packaging substrate includes an embedded metal inlay, vias in the packaging substrate and contacts on a bottom surface of the packaging substrate, each electrically coupled to a respective one of the vias. The method also includes forming a hybridized device, attaching a bottom surface of the hybridized device to a top surface of the metal inlay, and wirebonding a top surface of the hybridized device to a stop surface of the packaging substrate using a plurality of conductive connectors.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: June 28, 2022
    Assignee: Lumileds LLC
    Inventors: Tze Yang Hin, Seng Huat Lau, Hideo Kageyama
  • Patent number: 11374029
    Abstract: It is an object to manufacture and provide a highly reliable display device including a thin film transistor with a high aperture ratio which has stable electric characteristics. In a manufacturing method of a semiconductor device having a thin film transistor in which a semiconductor layer including a channel formation region is formed using an oxide semiconductor film, a heat treatment for reducing moisture and the like which are impurities and for improving the purity of the oxide semiconductor film (a heat treatment for dehydration or dehydrogenation) is performed. Further, an aperture ratio is improved by forming a gate electrode layer, a source electrode layer, and a drain electrode layer using conductive films having light transmitting properties.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: June 28, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Masayuki Sakakura
  • Patent number: 11362062
    Abstract: A semiconductor package includes a base chip and at least one semiconductor chip disposed on the base chip. An adhesive film is disposed between the base chip and the at least one semiconductor chip and is configured to fix the at least one semiconductor chip on the base chip. The adhesive film includes an inner film portion that overlaps the at least one semiconductor chip in a thickness direction of the base chip, and an outer film portion that does not overlap the at least one semiconductor chip in the thickness direction of the base chip. A width of the outer film portion in a direction perpendicular to a lateral edge of the at least one semiconductor chip is substantially uniform within a deviation range of 20% of an average width of the outer film portion.
    Type: Grant
    Filed: January 5, 2021
    Date of Patent: June 14, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jihwan Hwang, Unbyoung Kang, Sangsick Park, Jihwan Suh, Soyoun Lee, Teakhoon Lee
  • Patent number: 11355619
    Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.
    Type: Grant
    Filed: March 31, 2020
    Date of Patent: June 7, 2022
    Assignee: Marlin Semiconductor Limited
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
  • Patent number: 11355438
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, a microelectronic device package may include a redistribution layer (RDL) and an interposer over the RDL. In an embodiment, a glass core may be formed over the RDL and surround the interposer. In an embodiment, the microelectronic device package may further comprise a plurality of dies over the interposer. In an embodiment, the plurality of dies are communicatively coupled with the interposer.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Rahul Manepalli, Gang Duan
  • Patent number: 11348873
    Abstract: A wafer stacking method and structure are provided. The wafer stacking method includes: providing a first wafer having an upper surface comprising a first bonding pad configured to connect to a first signal; fabricating a first lower redistribution layer (RDL) and a first upper RDL on the first wafer, with the first lower RDL including a first wiring connected to the first bonding pad, the first upper RDL including a second wiring connected to the first wiring, and the second wiring having a first landing pad; bonding a second wafer on the first upper RDL, wherein an upper surface of the second wafer includes a second bonding pad configured to connect to a second signal and located corresponding to the first bonding pad; and fabricating a first through silicon via (TSV) connected to the first landing pad. The wafer stacking method improves the manufacturing yield of a die.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: May 31, 2022
    Assignee: Changxin Memory Technologies, Inc.
    Inventors: Ling-Yi Chuang, Shu-Liang Ning
  • Patent number: 11342310
    Abstract: A semiconductor chip including a semiconductor substrate having a first surface and a second surface and having an active layer in a region adjacent to the first surface, a first through electrode penetrating at least a portion of the semiconductor substrate and connected to the active layer, a second through electrode located at a greater radial location from the center of the semiconductor substrate than the first through electrode, penetrating at least a portion of the semiconductor substrate, and connected to the active layer. The semiconductor chip also including a first chip connection pad having a first height and a first width, located on the second surface of the semiconductor substrate, and connected to the first through electrode, and a second chip connection pad having a second height greater than the first height and a second width greater than the first width, located on the second surface of the semiconductor substrate, and connected to the second through electrode.
    Type: Grant
    Filed: February 10, 2021
    Date of Patent: May 24, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yongwon Choi, Wonkeun Kim, Inyoung Lee
  • Patent number: 11342218
    Abstract: Systems, methods, and apparatus are provided for single crystalline silicon stack formation and bonding to a complimentary metal oxide semiconductor (CMOS) wafer for formation of vertical three dimensional (3D) memory. An example method for forming arrays of vertically stacked layers for formation of memory cells includes providing a silicon substrate, forming a layer of single crystal silicon germanium onto a surface of the substrate, epitaxially growing the silicon germanium to form a thicker silicon germanium layer, forming a layer of single crystal silicon onto a surface of the silicon germanium, epitaxially growing the silicon germanium to form a thicker silicon layer, and forming, in repeating iterations, layers of silicon germanium and silicon to form a vertical stack of alternating silicon and silicon germanium layers.
    Type: Grant
    Filed: November 2, 2020
    Date of Patent: May 24, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Si-Woo Lee, Byung Yoon Kim
  • Patent number: 11335772
    Abstract: Provided is a semiconductor device including a semiconductor substrate doped with impurities, a front surface-side electrode provided on a front surface side of the semiconductor substrate, a back surface-side electrode provided on a back surface side of the semiconductor substrate, wherein the semiconductor substrate has a peak region arranged on the back surface side of the semiconductor substrate and having one or more peaks of impurity concentration, a high concentration region arranged closer to the front surface than the peak region and having a gentler impurity concentration than the one or more peaks, and a low concentration region arranged closer to the front surface than the high concentration region and having a lower impurity concentration than the high concentration region.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: May 17, 2022
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takahiro Tamura, Yuichi Onozawa, Takashi Yoshimura, Hiroshi Takishita, Akio Yamano
  • Patent number: 11328937
    Abstract: Embodiments of the invention include device packages and methods of forming such packages. In an embodiment, the method of forming a device package may comprise forming a reinforcement layer over a substrate. One or more openings may be formed through the reinforcement layer. In an embodiment, a device die may be placed into one of the openings. The device die may be bonded to the substrate by reflowing one or more solder bumps positioned between the device die and the substrate. Embodiments of the invention may include a molded reinforcement layer. Alternative embodiments include a reinforcement layer that is adhered to the surface of the substrate with an adhesive layer.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: May 10, 2022
    Assignee: Intel Corporation
    Inventors: Omkar G. Karhade, Nitin A. Deshpande, Debendra Mallik, Bassam M. Ziadeh, Yoshihiro Tomita
  • Patent number: 11329124
    Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation element over the magnetic element. The isolation element partially covers a top surface of the magnetic element. The semiconductor device structure further includes a conductive line over the isolation element. In addition, the semiconductor device structure includes a dielectric layer over the conductive line and the magnetic element.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chin-Yu Ku, Chi-Cheng Chen, Hon-Lin Huang, Wei-Li Huang, Chun-Yi Wu, Chen-Shien Chen
  • Patent number: 11329142
    Abstract: A method for manufacturing a semiconductor device includes forming a fin on a semiconductor substrate, and forming a bottom source/drain region adjacent a base of the fin. In the method, a dielectric layer, a work function metal layer and a first gate metal layer are sequentially deposited on the bottom source/drain region and around the fin. The dielectric layer, the work function metal layer and the first gate metal layer form a gate structure. The method also includes removing the dielectric layer, the work function metal layer and the first gate metal layer from an end portion of the fin, and depositing a second gate metal layer around the end portion of the fin in place of the removed dielectric layer, the removed work function metal layer and the removed first gate metal layer. The second gate metal layer contacts the end portion of the fin.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: May 10, 2022
    Assignee: International Business Machines Corporation
    Inventors: Alexander Reznicek, Tak H. Ning, Bahman Hekmatshoartabari, Jeng-Bang Yau
  • Patent number: 11328981
    Abstract: The present disclosure includes a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate including a first area and a second area, a vertical insulating film passing through the substrate between the first area of the substrate and the second area of the substrate, an interlayer insulating structure disposed on the substrate, and a conductive pad formed on the interlayer insulating structure and overlapping the first area of the substrate. The semiconductor device &so includes a through electrode passing through the conductive pad, the interlayer insulating structure, and the substrate in the first area.
    Type: Grant
    Filed: October 20, 2020
    Date of Patent: May 10, 2022
    Assignee: SK hynix Inc.
    Inventor: Nam Jae Lee
  • Patent number: 11322433
    Abstract: In some examples, a package comprises first and second terminals and a conductive pathway coupling the first and second terminals. The conductive pathway is configured to generate a magnetic field. The package comprises a conductive member aligned with and coupled to the conductive pathway. The conductive pathway and the conductive member have a common shape. The package also comprises an insulative layer coupled to the conductive member and a die coupled to the insulative layer and having a circuit configured to measure the magnetic field. The circuit faces the conductive pathway.
    Type: Grant
    Filed: April 7, 2020
    Date of Patent: May 3, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Enis Tuncer, Alejandro Hernandez-Luna
  • Patent number: 11322368
    Abstract: A method for fabricating a semiconductor package, the method including: forming a release layer on a first carrier substrate, wherein the release layer includes a first portion and a second portion, wherein the first portion has a first thickness, and the second portion has a second thickness thicker than the first thickness; forming a barrier layer on the release layer; forming a redistribution layer on the barrier layer, wherein the redistribution layer includes wirings and an insulating layer; mounting a semiconductor chip on the redistribution layer; forming a molding layer on the redistribution layer to at least partially surround the semiconductor chip; attaching a second carrier substrate onto the molding layer; removing the first carrier substrate and the release layer; removing the barrier layer; and attaching a solder ball onto the redistribution layer exposed by removal of the barrier layer and the second portion of the release layer.
    Type: Grant
    Filed: September 29, 2020
    Date of Patent: May 3, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Ho Park, Jin-Woo Park, Seok Hyun Lee, Jae Gwon Jang, Gwang Jae Jeon
  • Patent number: 11322408
    Abstract: A method of forming a semiconductor structure includes forming a semiconductor layer stack including a substrate and a nanosheet channel stack including alternating layers of a sacrificial material and a semiconducting material providing nanosheet channels for nanosheet field-effect transistors. The method also includes forming vertical fins in the semiconductor layer stack, forming a liner on sidewalls of the vertical fins, and forming a sacrificial epitaxial layer over the substrate surrounding the vertical fins. The method further includes replacing the sacrificial epitaxial layer with a first dielectric layer, removing the liner to form air gaps between the first dielectric layer and sidewalls of the vertical fins, and forming a second dielectric layer in the air gaps between the first dielectric layer and sidewalls of the vertical fins. The first and second dielectric layers provide shallow trench isolation regions surrounding sidewalls of the vertical fins below the nanosheet channel stack.
    Type: Grant
    Filed: December 22, 2020
    Date of Patent: May 3, 2022
    Assignee: International Business Machines Corporation
    Inventors: Nicolas Loubet, Richard A. Conti, ChoongHyun Lee
  • Patent number: 11309292
    Abstract: A semiconductor device, the device including: a first silicon layer including a first single crystal silicon; a first metal layer over the first silicon layer; a second metal layer over the first metal layer; a first level including a plurality of transistors over the second metal layer, where the plurality of transistors include a second single crystal silicon; a third metal layer over the first level; a fourth metal layer over the third metal layer, where the fourth metal layer is aligned to the first metal layer with less than 40 nm alignment error; and a via disposed through the first level, where the via has a diameter of less than 450 nm.
    Type: Grant
    Filed: November 27, 2021
    Date of Patent: April 19, 2022
    Assignee: MONOLITHIC 3D INC.
    Inventors: Zvi Or-Bach, Brian Cronquist