Patents Examined by Thao X. Le
  • Patent number: 11973034
    Abstract: Exemplary methods of electroplating a metal with a nanotwin crystal structure are described. The methods may include plating a metal material into at least one opening on a patterned substrate, where at least a portion of the metal material is characterized by a nanotwin crystal structure. The methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nanotwin crystal structure. In additional examples, the nanotwin-phased metal may be nanotwin-phased copper.
    Type: Grant
    Filed: August 25, 2021
    Date of Patent: April 30, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Eric J. Bergman, John L. Klocke, Marvin L. Bernt, Jing Xu, Kwan Wook Roh
  • Patent number: 11961856
    Abstract: An image sensing device includes a first unit pixel block, a second unit pixel block, and an isolation transistor. The first unit pixel block includes a first common floating diffusion node, first photoelectric conversion elements, first transfer transistors and a first conversion gain transistor configured to change capacitance of the first common floating diffusion node. The second unit pixel block adjacent to the first unit pixel block includes a second common floating diffusion node, second photoelectric conversion elements, second transfer transistors and a second conversion gain transistor configured to change capacitance of the second common floating diffusion node. The isolation transistor located in a boundary region between the first unit pixel block and the second unit pixel block isolates the first conversion gain transistor and the second conversion gain transistor from each other.
    Type: Grant
    Filed: June 3, 2021
    Date of Patent: April 16, 2024
    Assignee: SK HYNIX INC.
    Inventor: Pyong Su Kwag
  • Patent number: 11943915
    Abstract: A three-dimensional memory device includes a lower stack and an upper stack stacked one on the other, and each including a plurality of word lines which are stacked alternately with a plurality of interlayer dielectric layers, wherein each of the lower stack and the upper stack includes a first cell part, a second cell part, a coupling part which couples the first cell part and the second cell part, and a staircase part which extends parallel to the coupling part from the first cell part and in which pad areas of the word lines are disposed in a stepwise manner, and wherein the coupling part of the upper stack is disposed to overlap with the staircase part of the lower stack, and the staircase part of the upper stack is disposed to overlap with the coupling part of the lower stack.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: March 26, 2024
    Assignee: SK hynix Inc.
    Inventor: Sung Lae Oh
  • Patent number: 11923409
    Abstract: A semiconductor device includes a source/drain feature over a semiconductor substrate, channel layers over the semiconductor substrate and connected to the source/drain feature, a gate portion between vertically adjacent channel layers, and an inner spacer between the source/drain feature and the gate portion and between adjacent channel layers. The semiconductor device further includes an air gap between the inner spacer and the source/drain feature.
    Type: Grant
    Filed: August 5, 2021
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Yu Lin, Wei-Yang Lee, Chia-Pin Lin, Tzu-Hua Chiu, Kuan-Hao Cheng, Wei-Han Fan, Li-Li Su, Wei-Min Liu
  • Patent number: 11923313
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: March 5, 2024
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11837614
    Abstract: A subpixel including at least one second-conductivity-type pinned photodiode layer that forms a p-n junction with a substrate semiconductor layer, at least one floating diffusion region, and at least one transfer gate stack structure. The at least one transfer gate stack structure may at least partially laterally surround the at least one second-conductivity-type pinned photodiode layer with a total azimuthal extension angle in a range from 240 degrees to 360 degrees around a geometrical center of the second-conductivity-type pinned photodiode layer. The at least one transfer gate stack structure may include multiple edges that overlie different segments of a periphery of the at least one second-conductivity-type pinned photodiode layer, and the floating diffusion region includes a portion located between the first edge and the second edge. In addition, multiple transfer gate stack structures and multiple floating diffusion regions may be present in the subpixel.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: December 5, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Feng-Chien Hsieh, Yun-Wei Cheng, Wei-Li Hu, Kuo-Cheng Lee, Hsin-Chi Chen
  • Patent number: 11837629
    Abstract: Semiconductor devices include a semiconductor layer structure comprising a drift region that includes a wide band-gap semiconductor material. A shielding pattern is provided in an upper portion of the drift region in an active region of the device and a termination structure is provided in the upper portion of the drift region in a termination region of the device. A gate trench extends into an upper surface of the semiconductor layer structure. The semiconductor layer structure includes a semiconductor layer that extends above and at least partially covers the termination structure.
    Type: Grant
    Filed: November 19, 2020
    Date of Patent: December 5, 2023
    Assignee: Wolfspeed, Inc.
    Inventors: Daniel J. Lichtenwalner, Edward R. Van Brunt, Brett Hull
  • Patent number: 11825683
    Abstract: This organic EL device (100) has a substrate (1), a drive circuit layer (2), a first inorganic protective layer (2Pa), an organic planarizing layer (2Pb), an organic EL element layer (3), a second inorganic protective layer (2Pa2), and a TFE structure (10). The TFE structure has a first inorganic barrier layer (12), an organic barrier layer (14), and a second inorganic barrier layer (16). When viewed from a normal line of the substrate, the organic planarizing layer is formed within a region where the first inorganic protective layer is formed, while an organic EL element is disposed within a region where the organic planarizing layer is formed. The TFE structure has an exterior edge which intersects with a lead-out line (32) and which is situated between an exterior edge of the organic planarizing layer and an exterior edge of the first inorganic protective layer.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: November 21, 2023
    Assignee: SAKAI DISPLAY PRODUCTS CORPORATION
    Inventors: Katsuhiko Kishimoto, Yozo Narutaki
  • Patent number: 11805702
    Abstract: A perpendicular magnetoresistive element comprises (counting from the element bottom): a reference layer having magnetic anisotropy in a direction perpendicular to a film surface and having an invariable magnetization direction; a tunnel barrier layer; a crystalline recording layer having magnetic anisotropy in a direction perpendicular to a film surface and having a variable magnetization direction; an oxide buffer layer; and a cap layer, wherein the crystalline recording layer consists of a CoFe alloy that is substantially free of boron and has BCC (body-centered cubic) CoFe grains having epitaxial growth with (100) plane parallel to a film surface.
    Type: Grant
    Filed: May 6, 2021
    Date of Patent: October 31, 2023
    Inventors: Yimin Guo, Rongfu Xiao, Jun Chen
  • Patent number: 11791271
    Abstract: An additional set of interconnects is created in bulk material, allowing connections to active devices to be made from both above and below. The interconnects below the active devices can form a power distribution network, and the interconnects above the active devices can form a signaling network. Various accommodations can be made to suit different applications, such as encapsulating buried elements, using sacrificial material, and replacing the bulk material with a dielectric. Epitaxial material can be used throughout the formation process, allowing for the creation of a monolithic substrate.
    Type: Grant
    Filed: May 3, 2021
    Date of Patent: October 17, 2023
    Assignee: Tokyo Electron Limited
    Inventors: Daniel Chanemougame, Lars Liebmann, Jeffrey Smith
  • Patent number: 11764238
    Abstract: An image sensing device is provided to include a pixel array of unit pixels, each pixel structured to respond to incident light to produce photocharges and including different photosensing sub-pixels at different locations within the unit pixel to detect incident light, different detection structures formed at peripheral locations of the different photosensing sub-pixels of the unit pixel, respectively, and configured to receive the photocharges that are generated by the different photosensing sub-pixels of and are carried by a current in the unit pixel, a unit pixel voltage node located at a center portion of the unit pixel and electrically coupled to electrically bias an electrical potential of the different photosensing sub-pixels, and a control circuit coupled to the different detection structures of the unit pixel to supply sub-pixel detection control signals to the different detection structures of the unit pixel, respectively.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: September 19, 2023
    Assignee: SK HYNIX INC.
    Inventors: Jae Hyung Jang, Hyung June Yoon, Jong Chae Kim, Hoon Moo Choi
  • Patent number: 11756964
    Abstract: A method for etching an insulating layer includes: sequentially forming a first gate insulating layer, an amorphous silicon layer, a first interlayer insulating layer, and a second interlayer insulating layer on a substrate; applying a photoresist on the second interlayer insulating layer, and patterning the photoresist through a photo-process; first etching the second interlayer insulating layer and the first interlayer insulating layer until at least a portion of the amorphous silicon layer is exposed by using the patterned photoresist as a mask; second etching the second interlayer insulating layer and the first interlayer insulating layer; third etching the amorphous silicon layer; and fourth etching the first gate insulating layer, wherein an etching gas used in the second etching includes a material having a higher etching selection ratio of the first and second interlayer insulating layers to the amorphous silicon layer than an etching gas used in the first etching.
    Type: Grant
    Filed: March 25, 2021
    Date of Patent: September 12, 2023
    Assignee: Samsung Display Co., Ltd.
    Inventors: Dae Soo Kim, Yu-Gwang Jeong, Sung Won Cho
  • Patent number: 11744070
    Abstract: A semiconductor memory device comprises: first conductive layers arranged in a first direction; a first semiconductor layer facing the first conductive layers; a second semiconductor layer facing the first conductive layers; second conductive layers arranged in the first direction; third conductive layers arranged in the first direction; a third semiconductor layer facing the second conductive layers and connected to the first semiconductor layer; a fourth semiconductor layer facing the third conductive layers and connected to the second semiconductor layer; a fourth conductive layer facing the third semiconductor layer; and a fifth conductive layer connected to the third conductive layers. A distance from a central axis of the third semiconductor layer to a central axis of the fourth semiconductor layer is larger than a distance from a central axis of the first semiconductor layer to a central axis of the second semiconductor layer.
    Type: Grant
    Filed: March 12, 2021
    Date of Patent: August 29, 2023
    Assignee: KIOXIA CORPORATION
    Inventors: Toshiya Murakami, Kenji Tashiro, Hidenori Miyagawa, Reiko Kitamura
  • Patent number: 11735615
    Abstract: An imaging device including: a photoelectric converter; a protection member provided on a light incidence side of the photoelectric converter; a substrate opposed to the protection member with the photoelectric converter interposed therebetween and having a first surface on the photoelectric converter side and a second surface opposed to the first surface; a rewiring layer provided in a selective region of the second surface of the substrate; and a protective resin layer provided on the second surface of the substrate, the second surface of the substrate having an external terminal coupling region exposed from the protective resin layer, and a stress relaxation region exposed from the protective resin layer and disposed at a position different from the external terminal coupling region.
    Type: Grant
    Filed: May 14, 2019
    Date of Patent: August 22, 2023
    Assignee: SONY SEMICONDUCTOR SOLUTIONS CORPORATION
    Inventors: Yoshiaki Masuda, Tokihisa Kaneguchi
  • Patent number: 11737274
    Abstract: A vertical memory structure comprises a stack of alternating layers of insulator material and word line material with a vertical opening through the alternating layers. One of the layers of insulating material and layers of word line material have recessed inside surfaces facing the opening. First and second conductive pillars are disposed inside the vertical opening. A data storage structure is disposed on the inside surfaces of the layers of word line material, including on the recessed inside surfaces. A semiconductor channel layer is disposed on the data storage structures around a perimeter of the vertical opening, and having first and second source/drain terminals at contacts with the first and second conductive pillars.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: August 22, 2023
    Assignee: MACRONIX INTERNATIONAL CO., LTD.
    Inventor: Kuan-Yuan Shen
  • Patent number: 11729974
    Abstract: A semiconductor memory device includes a word line extending in a vertical direction on a substrate, a channel layer surrounding the word line to configure a cell transistor and having a horizontal ring shape with a predetermined horizontal width, a bit line disposed at one end of the channel layer in a first horizontal direction and extending in a second horizontal direction perpendicular to the first horizontal direction, and a cell capacitor disposed at other end of the channel layer in the first horizontal direction, the cell capacitor including an upper electrode layer extending in the vertical direction, a lower electrode layer surrounding the upper electrode layer, and a capacitor dielectric layer disposed between the upper electrode layer and the lower electrode layer.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: August 15, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyunghwan Lee, Yongseok Kim, Hyuncheol Kim, Hyeoungwon Seo, Sungwon Yoo, Jaeho Hong
  • Patent number: 11730063
    Abstract: The magnetoresistive effect element includes a first ferromagnetic layer, a second ferromagnetic layer, and a nonmagnetic layer positioned between the first ferromagnetic layer and the second ferromagnetic layer, and at least one of the first ferromagnetic layer and the second ferromagnetic layer includes a Heusler alloy layer including a crystal region and an amorphous region.
    Type: Grant
    Filed: December 8, 2020
    Date of Patent: August 15, 2023
    Assignee: TDK CORPORATION
    Inventors: Kazuumi Inubushi, Katsuyuki Nakada, Shinto Ichikawa
  • Patent number: 11710704
    Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: July 25, 2023
    Assignee: Qorvo US, Inc.
    Inventors: Julio C. Costa, Michael Carroll
  • Patent number: 11678502
    Abstract: A display device includes a display panel having a display area comprising pixels and a non-display area surrounding the display area, an encapsulation substrate which faces the display panel and is disposed on a surface of the display panel, and a sealing member disposed in the non-display area and interposed between the display panel and the encapsulation substrate for bonding. The display panel comprises a base substrate and a first conductive layer disposed on a first surface of the base substrate, the base substrate provides a through hole defined in a part of the non-display area to penetrate the base substrate in a thickness direction, the first conductive layer comprises a signal line disposed in a part of the non-display area and filling the through hole, and the sealing member does not overlap the first conductive layer and the through hole in the thickness direction.
    Type: Grant
    Filed: September 4, 2020
    Date of Patent: June 13, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyun A Lee, Kyung Rok Ko, Yong Hoon Kwon, Byung Hoon Kim, Jung Hyun Kim, Tae Oh Kim, June Hyoung Park, Hyun Ji Lee, So Mi Jung
  • Patent number: 11626464
    Abstract: A display apparatus includes a substrate comprising a display area and a pad area located outside the display area. A plurality of date lines is in the display area. A plurality of connection wires is in the display area. The plurality of connection wires is connected to the plurality of data lines and is configured to transfer data signals from the pad area to the plurality of data lines. An insulating film covers the plurality of connection wires. Each of the plurality of connection wires comprises a plurality of branches that diverge from a body of each connection wire the insulating film comprises a protrusion in a gap between adjacent branches of the plurality of branches.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: April 11, 2023
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Jonghyun Yun, Junyoung Kim, Minjeong Park