Abstract: An image sensor includes a first chip that includes a pixel region and a pad region, and a second chip that is in contact with one surface of the first chip and includes circuits that drive the first chip. The first chip includes a first substrate, an interlayer insulating layer disposed between the first substrate and the second chip, first interconnection lines disposed in the interlayer insulating layer, a conductive pad disposed in the pad region between the second chip and the first interconnection lines, and a recess region formed in the pad region that penetrates the first substrate and the interlayer insulating layer and exposes the conductive pad.

Abstract: A method includes etching a first recess adjacent a first dummy gate stack and a first fin; etching a second recess adjacent a second dummy gate stack and a second fin; and epitaxially growing a first epitaxy region in the first recess. The method further includes depositing a first metal-comprising mask over the first dummy gate stack, over the second dummy gate stack, over the first epitaxy region in the first recess, and in the second recess; patterning the first metal-comprising mask to expose the first dummy gate stack and the first epitaxy region; epitaxially growing a second epitaxy region in the first recess over the first epitaxy region; and after epitaxially growing the second epitaxy region, removing remaining portions of the first metal-comprising mask.

Abstract: A display substrate, a method manufacturing thereof and a display device are provided, including a base film layer, a functional film layer and a partial display region with hole-forming areas dividing an island area for displaying and a bridge area for signal transmission. The display substrate further includes a separation structure on the base film layer in the bridge area, which separates a target functional film layer into first and second parts. The target function film layer includes any functional film layer formed at a side of the separation structure away from the base film layer, the first part includes a part of the target functional film layer located at a side of the separation structure away from the hole-forming area, and the second part includes a part of the target functional film layer located at a side of the separation structure near the hole-forming area.

Abstract: A method of making an integrated circuit includes steps of etching an opening in an insulating mask to expose a first dummy contact on a backside of the integrated circuit, depositing a conductive material into the opening, the conductive material contacting a sidewall of the first dummy contact, and recessing the conductive material to expose an end of the first dummy contact. The method also includes steps of depositing an insulating material over the conductive material in the opening, removing the first dummy contact from the insulating mask to form a first contact opening, and forming a first conductive contact in the first contact opening, the first conductive contact being electrically connected to the conductive material.

Abstract: A photoelectric conversion apparatus includes a pad, a first protection circuit provided on a first semiconductor substrate, and a second protection circuit provided on a second semiconductor substrate. The first semiconductor substrate, which includes a plurality of photoelectric conversion units each receiving incident light and generating signal charge, and the second semiconductor substrate, which includes at least one signal processing circuit that processes an input signal based on the generated signal charge, are laminated. The pad receives a power supply voltage as input from an outside of the photoelectric conversion apparatus. At least one of the first protection circuit or the second protection circuit is provided on an outside of a region in which the pad is provided, in planar view. At least one of the first protection circuit or the second protection circuit is connected to the pad.

Abstract: There are provided a semiconductor memory device and a manufacturing method of the semiconductor including: a plurality of source channels penetrating a source select line; a gate stack structure overlapping with the source select line; a connection pattern disposed between the source select line and the gate stack structure, the connection pattern being commonly connected to the plurality of source channels; and a plurality of vertical channels penetrating the gate stack structure, the plurality of vertical channels being commonly connected to the connection pattern.

Abstract: Embodiments of the application provide a display panel, a display screen and a display device. The display panel includes a backplane, a color filter layer, and a black matrix between the backplane and the color filter layer. The backplane includes a base substrate, the color filter layer includes a plurality of sub-pixel color filters, and the plurality of sub-pixel color filters are arranged along a plane of the color filter layer and spliced together to form the color filter layer.

Abstract: A crosstalk-suppressing image sensor includes a semiconductor substrate, an opaque layer, and a spectral filter. The semiconductor substrate includes a photodiode therein and is located beneath a light-exposure region of a back surface of the semiconductor substrate. The opaque layer is on the back surface, partially covers the light-exposure region, and has an opaque-layer thickness perpendicular to an image-plane direction parallel to the back surface. The spectral filter is adjacent to the opaque layer in the image-plane direction, and partially covers the light-exposure region.

Abstract: A method for transferring a useful layer from a donor substrate to a carrier substrate comprises: a) providing the donor substrate, the donor substrate including a buried weakened plane; b) providing the carrier substrate; c) joining the donor substrate to the carrier substrate to form a bonded structure; and d) annealing the bonded structure in order to increase the level of weakening of the buried weakened plane. A predetermined stress is applied to the buried weakened plane during the annealing for a period of time, the predetermined stress being selected so as to initiate the splitting wave once a given level of weakening has been reached. At the end of the period of time, the given level of weakening having been reached, the predetermined stress causes initiation and self-sustained propagation of the splitting wave along the buried weakened plane, resulting in the useful layer being transferred to the carrier substrate.

Abstract: A semiconductor structure includes semiconductor devices located over a substrate, bit lines electrically connected to the semiconductor devices and having a respective reentrant vertical cross-sectional profile within a vertical plane that is perpendicular to a lengthwise direction along which the bit lines laterally extend, and dielectric portions that are interlaced with the bit lines along a horizontal direction that is perpendicular to the lengthwise direction. The dielectric portions may contain air gaps. A bit-line-contact via structure can be formed on top of a bit line. In some embodiments, dielectric cap strips may be located on top surface of the dielectric portions and may cover peripheral regions of the top surfaces of the bit lines without covering middle regions of the top surfaces of the bit lines.

Abstract: A method includes forming a 2-D material semiconductor layer over a substrate; forming source/drain electrodes covering opposite sides of the 2-D material semiconductor layer, while leaving a portion of the 2-D material semiconductor layer exposed by the source/drain electrodes; forming a first gate dielectric layer over the portion of the 2-D material semiconductor layer by using a physical deposition process; forming a second gate dielectric layer over the first gate dielectric layer by using a chemical deposition process, in which a thickness of the first gate dielectric layer is less than a thickness of the second gate dielectric layer; and forming a gate electrode over the second gate dielectric layer.

Abstract: An image sensor comprises a first photodiode region and circuitry. The first photodiode region is disposed within a semiconductor substrate proximate to a first side of the semiconductor substrate to form a first pixel. The first photodiode region includes a first segment coupled to a second segment. The circuitry includes at least a first electrode associated with a first transistor. The first electrode is disposed, at least in part, between the first segment and the second segment of the first photodiode region such that the circuity is at least partially surrounded by the first photodiode region when viewed from the first side of the semiconductor substrate.

Abstract: Provided is a display device which comprises a substrate, a plurality of pixels disposed on the substrate, a first initialization voltage line disposed on the substrate along a first direction, and a second initialization voltage line disposed on a different layer from the first initialization voltage line, wherein the second initialization voltage line may include a horizontal portion disposed along the first direction and a vertical portion disposed along a second direction crossing the first direction, and the vertical portion may be disposed between a plurality of pixels adjacent to each other in the first direction.

Abstract: An organic light-emitting display device includes a substrate having a display region and a peripheral region, a plurality of pixels on the substrate in the display region, a first wiring and a second wiring on the substrate in the peripheral region, An insulation layer on the first and second wirings, the insulation layer covering a top surface and a sidewall of each of the first and second wirings, and an encapsulation layer on the plurality of pixels and on the insulation layer.

Abstract: There are provided a memory device and a manufacturing method of the memory device. The memory device includes: a first gate conductive pattern including a first horizontal part and a second horizontal part and a third horizontal part connected to one end portion of the first horizontal part; a first insulating pattern disposed between the first horizontal part and the second horizontal part of the first gate conductive pattern; and a second gate conductive pattern including a first horizontal part and a second horizontal part and a third horizontal part connected to one end portion of the second horizontal part of the second gate conductive pattern; a first gate contact structure extending vertically on a contact region, the first gate contact structure being in contact with the first gate conductive pattern while penetrating the third horizontal part of the first gate conductive pattern.

Abstract: A micro light emitting diode including an epitaxy layer, a first pad, a second pad, a first ohmic contact metal, a second ohmic contact metal and at least one etch protection conductive layer is provided. The first pad and the second pad are electrically connected to a first type semiconductor layer and a second type semiconductor layer of the epitaxy layer, respectively. The first ohmic contact metal is disposed between the first type semiconductor layer and the first pad. The second ohmic contact metal is disposed between the second type semiconductor layer and the second pad. The at least one etch protection conductive layer is disposed between the first ohmic contact metal and the first pad and/or between the second ohmic contact metal and the second pad. A display panel is also provided.

Abstract: Exemplary methods of electroplating a metal with a nanotwin crystal structure are described. The methods may include plating a metal material into at least one opening on a patterned substrate, where at least a portion of the metal material is characterized by a nanotwin crystal structure. The methods may further include polishing an exposed surface of the metal material in the opening to reduce an average surface roughness of the exposed surface to less than or about 1 nm. The polished exposed surface may include at least a portion of the metal material characterized by the nanotwin crystal structure. In additional examples, the nanotwin-phased metal may be nanotwin-phased copper.

Abstract: An image sensing device includes a first unit pixel block, a second unit pixel block, and an isolation transistor. The first unit pixel block includes a first common floating diffusion node, first photoelectric conversion elements, first transfer transistors and a first conversion gain transistor configured to change capacitance of the first common floating diffusion node. The second unit pixel block adjacent to the first unit pixel block includes a second common floating diffusion node, second photoelectric conversion elements, second transfer transistors and a second conversion gain transistor configured to change capacitance of the second common floating diffusion node. The isolation transistor located in a boundary region between the first unit pixel block and the second unit pixel block isolates the first conversion gain transistor and the second conversion gain transistor from each other.

Abstract: A three-dimensional memory device includes a lower stack and an upper stack stacked one on the other, and each including a plurality of word lines which are stacked alternately with a plurality of interlayer dielectric layers, wherein each of the lower stack and the upper stack includes a first cell part, a second cell part, a coupling part which couples the first cell part and the second cell part, and a staircase part which extends parallel to the coupling part from the first cell part and in which pad areas of the word lines are disposed in a stepwise manner, and wherein the coupling part of the upper stack is disposed to overlap with the staircase part of the lower stack, and the staircase part of the upper stack is disposed to overlap with the coupling part of the lower stack.

Abstract: The present disclosure relates to a radio frequency (RF) device that includes a mold device die and a multilayer redistribution structure underneath the mold device die. The mold device die includes a device region with a back-end-of-line (BEOL) portion and a front-end-of-line (FEOL) portion over the BEOL portion, and a first mold compound. The FEOL portion includes an active layer, a contact layer, and isolation sections. Herein, the active layer and the isolation sections reside over the contact layer, and the active layer is surrounded by the isolation sections. The first mold compound resides over the active layer without silicon crystal, which has no germanium content, in between. The multilayer redistribution structure includes redistribution interconnections and a number of bump structures that are at bottom of the multilayer redistribution structure and electrically coupled to the mold device die via the redistribution interconnections.