Abstract: An active matrix light emitting display comprising an anode layer comprising a plurality of individual selectively energizable anodes, a cathode layer comprising a plurality of individual selectively energizable cathodes, an emitter layer for emitting light when energized disposed between the anode layer and the cathode layer, and a photoluminescent layer comprising a plurality of various color photoluminescent pixels, wherein a selected anode and a selected cathode are energizable to photoexcite a selected color pixel. A light emitting device comprising, a light emitting photonic crystal having organic electroluminescent emitter material disposed within the photonic crystal, and a photoluminescent material disposed upon a surface of the light emitting photonic crystal, such that light emitted by the light emitting photonic crystal causes photoexcitation within the photoluminescent material.

Abstract: Disclosed herein is an organic lighting apparatus that can reduce leakage current. The organic lighting apparatus includes a plurality of light-emitting portions, each of which has a first electrode including an electric current injection line, wherein the electric current injection line includes one or more fuse structures. With the electric current injection line including a fuse structure, when a short circuit occurs between first and second electrodes in a specific light-emitting portion, the fuse operates and prevents electric current from being injected into the short-circuited light-emitting portion, thereby making it possible to reduce leakage current.

Abstract: Semiconductor devices are provided. A semiconductor device includes a substrate including a device region defined by a trench in the substrate. The semiconductor device includes a plurality of fin-shaped active regions spaced apart from each other in the device region and extending in a first direction. The semiconductor device includes a protruding pattern extending along a bottom surface of the trench. Moreover, an interval between the protruding pattern and the plurality of fin-shaped active regions is greater than an interval between two adjacent ones of the plurality of fin-shaped active regions.

Abstract: Provided is a semiconductor device that includes a semiconductor substrate, an interconnection layer that is formed on a first face of the semiconductor substrate, at least one of a structural element that is formed to the interconnection layer, or a structural element that is formed in the semiconductor substrate from the first face side of the semiconductor substrate, a semiconductor-through-electrode that is positioned and formed, from a second face side of the semiconductor substrate opposite to the first face, so as to have a predetermined positional relationship with respect to the structural element, and a metallic-diffusion-preventing insulating layer that is formed from the first face side of the semiconductor substrate in a position, and with a shape, surrounding the semiconductor-through-electrode in the semiconductor substrate.

Abstract: The present invention concerns a sensitive field effect device (100) comprising a semiconductor channel (110), a source electrode (120) connected to said semiconductor channel (110), a drain electrode (130) connected to said semiconductor channel (110), such that said semiconductor channel (110) is interposed between said source electrode (120) and said drain electrode (130), a gate electrode (140) and a dielectric layer (150) interposed between said gate electrode (140) and said semiconductor channel (110), characterized in that said semiconductor channel (110) is a layer and is made of an amorphous oxide and in that said sensor means (170, 171, 172, 173, 174, 175, 175) are configured to change the voltage between said gate electrode (140) and said source electrode (120) upon a sensing event capable of changing their electrical state. The present invention also concerns a sensor and a method for manufacturing said field effect device (100).

Abstract: To suppress variation in transistor characteristics due to charging damage to relieve restrictions on design necessary for avoiding the charging damage and improve the degree of freedom in design for increasing semiconductor integration. A semiconductor device includes a vertical electrode formed in a vertical hole extending from an opening portion toward a portion to be connected in a thickness direction of a base, and having a structure in which a barrier metal film and a conductive material are stacked sequentially from a side close to an insulating film exposed to the vertical hole, and a low-resistance film provided to lie between the barrier metal film and the insulating film except a vicinity of the portion to be connected, and having a lower resistance value than a resistance value of the insulating film.

Abstract: According to various embodiments, there is provided a sensor device that includes: a substrate and two semiconductor structures. Each semiconductor structure includes a source region and a drain region at least partially disposed within the substrate, a channel region between the source region and the drain region, and a gate region. A first semiconductor structure of the two semiconductor structures further includes a sensing element electrically connected to the first gate structure. The sensing element is configured to receive a solution. The drain regions of the two semiconductor structures are electrically coupled. The source regions of the two semiconductor structures are also electrically coupled. A mobility of charge carriers of the channel region of a second semiconductor structure of the two semiconductor structures is lower than a mobility of charge carriers of the channel region of the first semiconductor structure.

Abstract: The present technology relates to a solid-state image capturing apparatus and an electronic device that can acquire a normal image and a narrow band image at the same time. The solid-state image capturing apparatus includes a plurality of substrates laminated in two or more layers, and two or more substrates of the plurality of substrates have pixels that perform photoelectric conversion. At least one substrate of the substrates having the pixels is a visible light sensor that receives visible light, and at least another substrate of the substrates having the pixels is a narrow band light sensor that includes narrow band filters being optical filters permeating light in a narrow wavelength band, and receives narrow band light in the narrow band.

Abstract: A method of manufacturing an organic light emitting diode (OLED) display device includes: providing a substrate including a display area and a non-display area; forming an organic light emitting diode element in the display area; forming a barrier wall around the display area and spaced apart from the organic light emitting diode element; performing a plasma treatment on the substrate on which the organic light emitting diode element is formed; and forming a thin film encapsulation layer for coating the organic light emitting diode element, wherein forming the thin film encapsulation layer includes: forming at least one inorganic layer; and forming at least one organic layer inwardly of the barrier wall.

Abstract: A method includes removing a dummy gate structure formed over a first fin and a second fin, forming an interfacial layer in the first trench and the second trench, forming a first high-k dielectric layer over the interfacial layer in the first trench and the second trench, removing the first high-k dielectric layer in the second trench, forming a self-assembled monolayer over the first high-k dielectric layer in the first trench, forming a second high-k dielectric layer over the self-assembled monolayer in the first trench and over the interfacial layer in the second trench, forming a work function metal layer in the first and the second trenches, and forming a bulk conductive layer over the work function metal layer in the first and the second trenches. In some embodiments, the first high-k dielectric layer includes lanthanum and oxygen.

Abstract: A display device includes a scan line extending in a first direction. A plurality of data lines cross the scan line. A driving voltage line crosses the scan line. An active pattern includes a plurality of channel regions and a plurality of conductive regions. A control line is connected to the plurality of data lines and the driving voltage line. The active pattern includes a shielding part overlapping at least one data line of the plurality of data lines. The control line includes a plurality of main line parts each extending in the first direction, and a detour part connecting two adjacent main line parts of the plurality of main line parts to each other. The detour part extends along a periphery of the active pattern and crosses the at least one data line of the plurality of data lines.

Abstract: A memory device includes a first bottom electrode, a first memory stack, and a second memory stack. The first bottom electrode has a first portion and a second portion connected to the first portion. The first memory stack is over the first portion of the first bottom electrode. The first memory stack includes a first resistive switching element and a first top electrode over the first resistive switching element. The second memory stack is over the second portion of the first bottom electrode. The second memory stack comprises a second resistive switching element and a second top electrode over the second resistive switching element.

Abstract: A device includes a first capacitor and a second capacitor connected to the first capacitor in parallel. The first capacitor includes a semiconductor region and a first plurality of gate stacks. The first plurality of gate stacks comprise a plurality of gate dielectrics over and contacting the semiconductor region, and a plurality of gate electrodes over the plurality of gate dielectrics. The second capacitor includes an isolation region, a second plurality of gate stacks over the isolation region, and a plurality of conductive strips over the isolation region and parallel to the second plurality of gate stacks. The second plurality of gate stacks and the plurality of conductive strips are laid out alternatingly.

Abstract: In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing a Pad on Solder Mask (PoSM) semiconductor substrate package.

Abstract: An electroluminescent display apparatus includes: a substrate including: first to third subpixels, a circuit device layer including a driving thin-film transistor respectively in each of the first to third subpixels on the substrate, a first electrode respectively in each of the first to third subpixels, a light-emitting layer on the first electrodes, and a second electrode on the light-emitting layer, wherein the first electrode of the first subpixel includes: a first lower electrode, and a first upper electrode, wherein the first electrode of the second subpixel includes: a second lower electrode, and a second upper electrode, wherein a distance between the first lower electrode and the first upper electrode differs from a distance between the second lower electrode and the second upper electrode, and wherein the first lower electrode and the first upper electrode are electrically connected to each other through a first contact electrode therebetween.

Abstract: An apparatus for and a method of bonding a first substrate and a second substrate are provided. In an embodiment a first wafer chuck has a first curved surface and a second wafer chuck has a second curved surface. A first wafer is placed on the first wafer chuck and a second wafer is placed on a second wafer chuck, such that both the first wafer and the second wafer are pre-warped prior to bonding. Once the first wafer and the second wafer have been pre-warped, the first wafer and the second wafer are bonded together.

Abstract: A field-effect transistor includes a substrate; a source electrode, a drain electrode, and a gate electrode that are formed on the substrate; a semiconductor layer by which a channel is formed between the source electrode and the drain electrode when a predetermined voltage is applied to the gate electrode; and a gate insulating layer provided between the gate electrode and the semiconductor layer. The gate insulating layer is formed of an amorphous composite metal oxide insulating film including one or two or more alkaline-earth metal elements and one or two or more elements selected from a group consisting of Ga, Sc, Y, and lanthanoid except Ce.

Abstract: A semiconductor structure includes a semiconductor strip in a seal ring area. The semiconductor structure further includes a dielectric structure extending into the semiconductor strip, wherein a plurality of metal structures and a plurality of via structures stack over the dielectric structure to form a seal ring structure.

Abstract: An organic light-emitting display apparatus includes: a display unit including an organic light-emitting element, a driving transistor electrically connected to the organic light-emitting element, and a capacitor; and a pad unit connected to the display unit, the capacitor including: a first conductive layer disposed on a substrate; a second conductive layer interposed between the substrate facing a first surface of the first conductive layer; and a third conductive layer disposed facing a second surface of the first conductive layer opposing the first surface of the first conductive layer, the third conductive layer being electrically connected to the second conductive layer.

Abstract: Structures, methods and devices are disclosed, related to improved stack structures in electronic devices. In some embodiments, a stack structure includes a pad implemented on a substrate, the pad including a polymer layer having a side that forms an interface with another layer of the pad, the pad further including an upper metal layer over the interface, the upper metal layer having an upper surface. In some embodiments, the stack structure also includes a passivation layer implemented over the upper metal layer, the passivation layer including a pattern configured to provide a compressive force on the upper metal layer to thereby reduce the likelihood of delamination at the interface, the pattern defining a plurality of openings to expose the upper surface of the upper metal layer.