Abstract: The semiconductor device includes at least three semiconductor elements disposed directly or indirectly on a planar member and constituting an upper arm and a lower arm which perform ON and OFF action at mutually differential times; an upper-surface voltage applied region of each semiconductor element is configured to be narrower than an area of the aforementioned whole semiconductor element in planar view; and each semiconductor element is disposed so that the shortest distance between the semiconductor elements constituting the upper arm is formed so as to be longer than the shortest distance between the semiconductor element constituting the upper arm and the semiconductor element constituting the lower arm.

Abstract: An integrated circuit (IC) structure includes a power rail oriented in a power rail direction and first metal segments above the power rail, oriented in a first metal level direction perpendicular to the power rail direction. First vias positioned between the power rail and the first metal segments are positioned at locations where first metal segments overlap the power rail. A second metal segment is positioned above the first metal segments, overlaps the power rail, and is oriented in the power rail direction. Second vias are positioned above the first vias between the first metal segments and the second metal segments, and a power strap is positioned above the second metal segment. The power strap is electrically connected to the power rail, each first metal segment of the plurality of first metal segments has a minimum width, and the power strap has a width greater than a minimum width.

Abstract: An OLED display and a method of manufacturing thereof are disclosed. In one aspect, the display includes a scan line formed over a substrate and configured to transfer a scan signal, a data line and a driving voltage line crossing the scan line and respectively configured to transfer a data voltage and a driving voltage, and a switching transistor electrically connected to the scan line and the data line and including a switching drain electrode configured to output the data voltage. The display also includes a driving transistor including a driving gate electrode, a driving drain electrode, and a driving source electrode electrically connected to the switching drain electrode. The display further includes a storage capacitor including a first storage electrode electrically connected to the driving gate electrode and a second storage electrode formed on the same layer as the driving voltage line.

Abstract: A panel type fan-out wafer level package with embedded film type capacitors and resistors is described. The package comprises a silicon die at a bottom of the package wherein a top side and lateral sides of the silicon die are encapsulated in a molding compound, at least one redistribution layer connected to the silicon die through copper posts contacting a top side of the silicon die, at least one embedded capacitor material (ECM) sheet laminated onto the package, and at least one embedded resistor-conductor material (RCM) sheet laminated onto the package wherein the at least one redistribution layer, capacitors in the at least one ECM, and resistors in the at least one RCM are electrically interconnected.

Abstract: A silicon carbide semiconductor device includes plural p-type silicon carbide epitaxial layers provided on an n+-type silicon carbide substrate. In some of the p-type silicon carbide epitaxial layers, an n+ source region is provided in at least a region of an upper portion. The n+ source region includes a first portion that contains arsenic and a second portion that contains phosphorous.

Abstract: The present disclosure provides a device includes a first gate structure segment and a collinear second gate structure segment, as well as a third gate structure segment and a collinear fourth gate structure segment. An interconnection extends from the first gate structure segment to the fourth gate structure segment. The interconnection is disposed above the first gate structure segment and the fourth gate structure segment. The interconnection may be formed on or co-planar with a contact layer of the semiconductor device.

Abstract: Semiconductor structures having a nanocrystalline core and corresponding nanocrystalline shell and insulator coating, wherein the semiconductor structure includes an anisotropic nanocrystalline core composed of a first semiconductor material, and an anisotropic nanocrystalline shell composed of a second, different, semiconductor material surrounding the anisotropic nanocrystalline core. The anisotropic nanocrystalline core and the anisotropic nanocrystalline shell form a quantum dot. An insulator layer encapsulates the nanocrystalline shell and anisotropic nanocrystalline core.

Abstract: A display device includes a display panel including a lower surface, an upper surface facing the lower surface, and a first area, a first film positioned below the lower surface and provided with a film groove defined therein overlapping with the first area, a second film disposed on the upper surface, and an adhesive layer disposed between the lower surface of the display panel and the first film and provided with an adhesive groove defined therein overlapping with the first area. The first area extends across the display panel along a first direction, one side surface of the adhesive groove is defined by one line when viewed in a cross section taken along a second direction crossing the first direction, and one side surface of the film groove is defined by two or more lines when viewed in the cross section taken along the second direction.

Abstract: A method for fabricating a semiconductor device including vertical transport fin field-effect transistors (VTFETs) is provided. The method includes forming a bottom spacer on a first device region associated with a first VTFET and a second device region associated with a second VTFET, forming a liner on the bottom spacer, on a first fin structure including silicon germanium (SiGe) formed in the first device region and on a second fin structure including SiGe formed in the second device region, and forming crystalline Ge having a hexagonal structure from the SiGe by employing a Ge condensation process to orient a (111) direction of the crystalline Ge in a direction of charge flow for a VTFET.

Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.

Abstract: According to a method for producing a flexible OLED device of the present disclosure, a multilayer stack (100) is provided, the multilayer stack including a base (10), a functional layer region (20) which includes a TFT layer and an OLED layer, a flexible film (30) provided between the base and the functional layer region and supporting the functional layer region, and a release layer (12) provided between the flexible film and the base and bound to the base. The release layer is irradiated with lift-off light (216) transmitted through the base, whereby the flexible film is delaminated from the release layer. The release layer is made of an alloy of aluminum and silicon.

Abstract: Fin-based transistor structures, such as finFET and nanowire transistor structures, are disclosed. The fins have a morphology including a wave pattern and/or one or more ridges and/or nodules which effectively mitigate fin collapse, by limiting the inter-fin contact during a fin collapse condition. Thus, while the fins may temporarily collapse during wet processing, the morphology allows the collapsed fins to recover back to their uncollapsed state upon drying. The fin morphology may be, for example, an undulating pattern having peaks and troughs (e., sine, triangle, or ramp waves). In such cases, the undulating patterns of neighboring fins are out of phase, such that inter-fin contact during fin collapse is limited to peak/trough contact. In other embodiments, one or more ridges or nodules (short ridges), depending on the length of the fin, effectively limit the amount of inter-fin contact during fin collapse, such that only the ridges/nodules contact the neighboring fin.

Abstract: Provided is a light-emitting element which includes a first electrode, a second electrode over the first electrode, and first and second light-emitting layers therebetween. The first light-emitting layer contains a first host material and a first light-emitting material, and the second light-emitting layer contains a second host material and a second light-emitting material. The first light-emitting material is a fluorescent material, and the second light-emitting material is a phosphorescent material. The level of the lowest triplet excited state (T1 level) of the first light-emitting material is higher than the T1 level of the first host material. A light-emitting device, an electronic device, and a lighting device including the light-emitting element are further provided.

Abstract: A light-emitting device is disclosed, including: a substrate; a light-emitting diode (LED) formed on a first surface of the substrate, the LED being arranged to emit primary light; a fence disposed on a second surface of the substrate, the fence including a plurality of walls arranged to define a cell; a light-converting structure disposed in the cell, the light-converting structure being arranged to convert at least a portion of the primary light to secondary light having a wavelength that is different from the wavelength of the primary light; and a reflective element formed on one or more outer surfaces of the walls of the fence, such that the reflective element and the light-converting structure are disposed on opposite sides of the walls of the fence.

Abstract: Disclosed are a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a device isolation layer defining active regions of a substrate, and gate lines buried in the substrate and extending across the active regions. Each of the gate lines includes a conductive layer, a liner layer disposed between and separating the conductive layer and the substrate, and a first work function adjusting layer disposed on the conductive layer and the liner layer. The first work function adjusting layer includes a first work function adjusting material. A work function of the first work function adjusting layer is less than those of the conductive layer and the liner layer.

Abstract: An optical assembly and a display device are disclosed. In an embodiment an optical assembly includes a common carrier, a plurality of first chip groups, each first chip group comprising at least two similar luminescence diode chips, a plurality of second chip groups, each second chip group comprising at least two similar luminescence diode chips, wherein the first and second chip groups are arranged planar along a regular grid of first unit cells on a main surface of the common carrier and an optical element arranged downstream of the first and second chip groups with respect to a main radiation direction, wherein the luminescence diode chips of the different chip groups are configured to emit electromagnetic radiation of different wavelength characteristics.

Abstract: By using an a-Si layer with low electron mobility in a TFT for driving an organic EL display device, the present invention solves problems stemming from uneven laser irradiation and suppresses the occurrence of non-uniform color and luminance. In the present invention, a first conductor film (26a) forming a drain electrode and a second conductor film (25a) forming a source electrode are disposed such that respective portions (26a1 . . . , 25a1 . . . ) of the first conductor film (26a) and the second conductor film (25a) are arranged in an alternating manner along a prescribed direction.

Abstract: An organic light emitting diode display comprises a substrate comprising a major surface; first, second, third and fourth electrodes positioned over the substrate; a pixel defining layer positioned over the plurality of electrodes and comprising first, second, third and fourth openings; and a spacer positioned over the pixel defining layer. The first, second, third and fourth openings overlap the first, second, third and fourth electrodes, respectively, when viewed in a viewing direction perpendicular to the major surface. The first, second, third and fourth openings comprise first, second, third and fourth corners, respectively, wherein the first, second, third and fourth corners neighbor one another when viewed in the viewing direction. When viewed in the viewing direction, the spacer comprises at least a portion placed within an imaginary polygon defined by the first, second, third and fourth corners.

Abstract: A technique relates to a trilayer Josephson junction structure. A dielectric layer is on a base electrode layer that is on a substrate. A counter electrode layer is on the dielectric layer. First and second counter electrodes are formed from the counter electrode layer. First and second dielectric layers are formed from the dielectric layer. First and second base electrodes are formed from base electrode layer. The first counter electrode, first dielectric layer, and first base electrode form a first stack. The second counter electrode, second dielectric layer, and second base electrode form a second stack. A shunting capacitor is between first and second base electrodes. An ILD layer is deposited on the substrate, the first and second counter electrodes, and the first and second base electrodes. A contact bridge connects the first and second counter electrodes. An air gap is formed underneath the contact bridge by removing ILD.

Abstract: In a general aspect, a semiconductor device can include a semiconductor region of a first conductivity type and a well region of a second conductivity type. The well region can be disposed in the semiconductor region. An interface between the well region and the semiconductor region can define a diode junction at a depth below an upper surface of the semiconductor region. The semiconductor device can further include at least one dielectric region disposed in the semiconductor region. A dielectric region of the at least one dielectric region can have an upper surface that is disposed in the well region at a depth in the semiconductor region that is above the depth of the diode junction; and a lower surface that is disposed in the semiconductor region at a depth in the semiconductor region that is the same depth as the diode junction or below the depth of the diode junction.