Abstract: A method includes forming mask patterns spaced apart from each other by at least one opening on an etch target layer, filling the opening with a block copolymer material including first and second polymer blocks of different properties, and annealing the block copolymer material to form first patterns and second patterns, the first patterns in contact with facing sidewalls of adjacent ones of the mask patterns, respectively, and at least one of the second patterns between the first patterns. The first patterns include the first polymer blocks and the second patterns include the second polymer blocks.

Abstract: An electroluminescent device includes a first electrode and a second electrode facing each other, and an emissive layer disposed between the first electrode and the second electrode and including the quantum dots. The quantum dots include a semiconductor nanocrystal core including indium (In) and phosphorous (P), a first semiconductor nanocrystal shell disposed on the semiconductor nanocrystal core, the first semiconductor nanocrystal shell including zinc and selenium, and a second semiconductor nanocrystal shell disposed on the first semiconductor nanocrystal shell, the second semiconductor nanocrystal shell including zinc and sulfur, wherein the quantum dots do not include cadmium. The electroluminescent device has an external quantum efficiency of greater than or equal to about 9% and a maximum brightness of greater than or equal to about 10,000 candelas per square meter (cd/m2).

Abstract: The present disclosure describes patterned devices and methods for repairing substrate lattice damage in a patterned device. The patterned device includes a substrate, an alternating conductor and dielectric stack atop the substrate, a channel hole extending through the alternating conductor and dielectric stack to the substrate, and an epitaxial grown layer at a bottom of the channel hole and a top surface of the substrate. A part of the substrate in contact with the epitaxial grown layer has a dopant or doping concentration different from an adjacent part of the substrate. The method includes forming a channel hole in an insulating layer atop a substrate, forming an amorphous layer in a top side of the substrate below the channel hole, heating to crystallize the amorphous layer, and growing an epitaxial layer on the crystallized layer in the channel hole.

Abstract: A semiconductor device of an embodiment includes a substrate, first, second, third, and fourth semiconductor elements, a first wiring layer, and first and second bonding wires. The third semiconductor element is on the substrate between the first resin element and the second resin element. The first wiring layer is on the first semiconductor element, is connected to the first semiconductor element, and is connected to the substrate by the first bonding wire. The fourth semiconductor element is on the first wiring layer and is connected to the first wiring layer by a second bonding wire. The first bonding wire is at a side of the first wiring layer other than a side farthest from the second wiring layer.

Abstract: A semiconductor structure for a wide bandgap normally off MOSFET has a III-group nitride, a V-group nitride, or a high K material trapping layer disposed under a gate electrode. Through the FN tunneling effect or channel hot electron (CHE) effect, multiple electrons are trapped by the trapping layer and kept in the trapping layer. The electrons in the trapping layer deplete the two-dimensional electron gas (2DEG) below the trapping layer, and then the 2DEG below the gate electrode disappear.

Abstract: A semiconductor device includes a base, a stacked body, a plate-shaped portion, and first to third columnar portions. The stacked body is provided over the base. The plate-shaped portion is inside the stacked body from an upper end of the stacked body to the base. The first to third columnar portions are inside the stacked body from the upper end of the stacked body to the base. The second columnar portion is located away from the first columnar portion in a first direction. The third columnar portion is aligned with the first columnar portion and the second columnar portion in the first direction. A pitch between the third columnar portion and the first columnar portion is a first pitch. A pitch between the third columnar portion and the second columnar portion is a second pitch larger than the first pitch.

Abstract: A method for forming a semiconductor structure comprises heating a solid material to form a gaseous substance; ionizing the gaseous substance to produce a first type of ions; and implanting the first type of ions into a semiconductor substrate. The method can achieve better abruptness, better shallow junction depth, and better sheet resistance.

Abstract: A thin-film capacitor structure (50) is joined to an electrode pad surface (2S) of an area array integrated circuit (2) having a plurality of electrode pads (3G, 3P, 3S) arranged in an area array on the electrode pad surface (2S). The thin-film capacitor structure (50) includes a thin-film capacitor (10) including a first sheet electrode (11), a second sheet electrode (13), and a thin-film dielectric layer (12) formed between the first sheet electrode (11) and the second sheet electrode (12), a first insulating film (21), a second insulating film (22), and a plurality of through holes (30P, 30G, 30S). The plurality of through holes (30P, 30G, 30S) are bored from the first insulating film (21) to the second insulating film (22) through the thin-film capacitor (10) and formed in positions corresponding to the plurality of electrode pads (3G, 3P, 3S).

Abstract: A transistor with small parasitic capacitance can be provided. A transistor with high frequency characteristics can be provided. A semiconductor device including the transistor can be provided. Provided is a transistor including an oxide semiconductor, a first conductor, a second conductor, a third conductor, a first insulator, and a second insulator. The first conductor has a first region where the first conductor overlaps with the oxide semiconductor with the first insulator positioned therebetween; a second region where the first conductor overlaps with the second conductor with the first and second insulators positioned therebetween; and a third region where the first conductor overlaps with the third conductor with the first and second insulators positioned therebetween. The oxide semiconductor including a fourth region where the oxide semiconductor is in contact with the second conductor; and a fifth region where the oxide semiconductor is in contact with the third conductor.

Abstract: A semiconductor package includes a semiconductor chip having connection pads on one surface thereof, a first encapsulant covering at least portions of the semiconductor chip, and a connection structure disposed on the one surface of the semiconductor chip and including one or more redistribution layers electrically connected to the connection pads. A wiring structure is disposed on one surface of the first encapsulant opposing another surface of the first encapsulant facing towards the connection structure. The wiring structure has a passive component embedded therein, and includes one or more wiring layers electrically connected to the passive component. The one or more redistribution layers and the one or more wiring layers are electrically connected to each other.

Abstract: The present disclosure includes methods of forming, and semiconductor structures for, integrated computing structures formed on silicon. An example method includes forming, on a silicon semiconductor material, an integrated computing structure by forming a number of complementary metal-oxide-semiconductor (CMOS) devices including a plurality of materials, forming a non-volatile memory (NVM) device including a plurality of materials, and forming the plurality of materials of the CMOS devices and the plurality of materials of the NVM device from a plurality of same materials shared at a corresponding plurality of positions within the structure. A particular function is provided by each of the plurality of same materials at the corresponding plurality of positions.

Abstract: A fin field effect transistor (FinFET) device structure with dummy fin structures and method for forming the same are provided. The FinFET device structure includes an isolation structure over a substrate, and a first fin structure extended above the isolation structure. The FinFET device structure includes a second fin structure embedded in the isolation structure, and a liner layer formed on sidewalls of the first fin structures and sidewalls of the second fin structures. The FinFET device structure includes a material layer formed over the second fin structures, and the material layer and the isolation structure are made of different materials.

Abstract: An image sensor includes a plurality of photodiodes arranged in rows and columns of a pixel array that is disposed in a semiconductor substrate. Individual photodiodes of the pixel array are configured to receive incoming light through a backside of the semiconductor substrate. A front side of the semiconductor substrate is opposite from the backside. A plurality of deep trench isolation (DTI) structures are formed laterally with respect to the photodiodes on the backside of the semiconductor substrate. The plurality of DTI structures are arranged between adjacent photodiodes. A plurality of pillar structures extend from a metal grid proximate to the backside and is formed proximate to the backside and aligned with the DTI structures.

Abstract: A semiconductor device includes a first stacked body comprising first conductive layers and first insulating layers interposed therebetween, a first columnar portion comprising a first semiconductor layer extending in the first stacked body in the first direction and a first memory layer between the first semiconductor layer and the first conductive layers, a second stacked body comprising second conductive layers and second insulating layers interposed therebetween, and a second columnar portion comprising a second semiconductor layer extending in the second stacked body in the first direction and a second memory layer between the second semiconductor layer and the second conductive layers. The first columnar portion has a first diameter, and the second columnar portion has a second diameter, and each of the plurality of first conductive layers has a first film thickness, and each of the plurality of second conductive layers has a second film thickness.

Abstract: A multi-chip package includes a first die having temperature sensors and a second die. The first die generates temperature deviation information of m (m<n) bits based on temperature information of n bits produced by the temperature sensors. The first die provides the temperature deviation information of m bits rather than the temperature information of n bits to the second die. An internal operation of the second die is controlled using the temperature deviation information output by the first die.

Abstract: According to one embodiment, a semiconductor package includes a die pad, a semiconductor chip, a lead frame, and an insulating part. The semiconductor chip is provided on the die pad. The lead frame is separated from the die pad. The lead frame is electrically connected to a terminal of the semiconductor chip. The lead frame includes a first part and a second part disposed between the first part and the die pad. An upper surface of the first part is located below an upper surface of the second part. The insulating part is provided on the die pad, the semiconductor chip, and the second part. The insulating part seals the semiconductor chip.

Abstract: A method of forming a transistor device includes providing a drift layer having a first conductivity type, forming a first region in the drift layer, the first region having a second conductivity type that is opposite the first conductivity type, forming a body layer on the drift layer including the first region, forming a source layer on the body layer, forming a trench in the source layer and the body layer above the first region and extending into the first region, forming a gate insulator on the inner sidewall of the trench, and forming a gate contact on the gate insulator.

Abstract: A light receiving device includes a protective layer between first and second electrodes, a first semiconductor layer between the protective layer and the first electrode, the first semiconductor layer having first and second protruding portions, an insulating material between the first and second protruding portions and extending between the protective layer and the first semiconductor layer, a second semiconductor layer between the first protruding portion and the protective layer and between the first protruding portion and the insulating material, a third semiconductor layer between the second semiconductor layer and the protective layer and between the second semiconductor layer and the insulating material, a fourth semiconductor layer between the second protruding portion and the protective layer and between the second protruding portion and the insulating material, and a fifth semiconductor layer between the fourth semiconductor layer and the protective layer and between the fourth semiconductor layer

Abstract: A semiconductor device has bipolar transistors on a substrate. There is also an insulating film on the substrate, covering the bipolar transistors. On this insulating film is emitter wiring, sticking through openings in the insulating film (first openings) to be electrically coupled to the emitter layer of the bipolar transistors. On the emitter wiring is a protective film. On the protective film is a bump, sticking through an opening in the protective film (second opening) to be electrically coupled to the emitter wiring. In plan view, the second opening is included in the area that is inside the bump and outside the first openings.

Abstract: An embodiment is a device including a first fin extending from a substrate, a first gate stack over and along sidewalls of the first fin, a first gate spacer disposed along a sidewall of the first gate stack, and a first epitaxial source/drain region in the first fin and adjacent the first gate spacer. The first epitaxial source/drain region including a first epitaxial layer on the first fin, the first epitaxial layer including silicon and carbon, a second epitaxial layer on the first epitaxial layer, the second epitaxial layer having a different material composition than the first epitaxial layer, the first epitaxial layer separating the second epitaxial layer from the first fin, and a third epitaxial layer on the second epitaxial layer, the third epitaxial layer having a different material composition than the first epitaxial layer.