Abstract: A memory structure including a substrate, a first gate structure, a second gate structure, a first spacer, a second spacer, and a third spacer is provided. The first gate structure includes a first gate and a charge storage layer. The charge storage layer is disposed between the first gate and the substrate. The second gate structure is disposed on the substrate. The second gate structure includes a second gate. A height of the first gate is higher than a height of the second gate. The first spacer and the second spacer are respectively disposed on one sidewall and the other sidewall of the first gate structure. The first spacer is located between the first gate structure and the second gate structure. The third spacer is disposed on a sidewall of the first spacer and covers a portion of a top surface of the second gate.

Abstract: A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate.

Abstract: Provided is a radiation-tolerant unit MOSFET to block a leakage current path caused by a total ionizing dose effect and reduce influence of a current pulse generated due to a single event effect. The radiation-tolerant unit MOSFET includes a poly gate layer for designating a gate region and at least one dummy gate region, a source and a drain, and a P+ layer and a P-active layer for specifying a P+ region to the source and the drain, and a dummy drain allowing application of a voltage. An electronic part that may normally operate is provided even a radiation environment where particle radiation and electromagnetic radiation are present.

Abstract: An optical structure has a cavity (1) with an opening provided at one end and a first through hole or first gap (21) provided at the end opposite the opening. The cavity is further provided internally with a beam splitter or a dichroic mirror (4). A first LED (31) emits light into the cavity through the first through hole or the first gap, which passes directly passing through the beam splitter or dichroic mirror and exits from the opening of the cavity A second LED (32) emits light into the cavity through a second through hole or second gap (22) in a side of the cavity, which is reflected by the beam splitter or dichroic mirror. It is then fused with the light emitted by the first LED. The light emitted by the respective LEDs have an identical optical path length to the beam splitter or the dichroic mirror.

Abstract: According to one embodiment, a semiconductor device include first and second electrodes, first, second, third, fourth, fifth, and sixth semiconductor regions, a gate electrode, and an interconnect portion. The first semiconductor region is provided on the first electrode. The second semiconductor region is electrically connected to the first electrode and provided around the first semiconductor region. The third semiconductor region is provided on the first and second semiconductor regions. The fourth semiconductor region is provided on a portion of the third semiconductor region. The fifth semiconductor region is provided selectively on the fourth semiconductor region. The gate electrode opposes the fifth and fourth semiconductor regions, and the portion. The sixth semiconductor region is provided on another portion of the third semiconductor region. The second electrode is provided on the fourth and fifth semiconductor regions. The interconnect portion is electrically connected to the gate electrode.

Abstract: A time of flight sensor is disclosed. In one example, it includes a pixel array with pixels arranged in rows and columns. A global control circuit disposed along a first side of the pixel array outputs a global control signal to the pixels. The global control circuit has a clock tree structure that includes buffer circuits and driving circuits. A rolling control circuit disposed along a second side of the pixel array outputs a rolling control signal to the pixels. A column circuit with analog-to-digital converters is coupled to the pixels.

Abstract: A method of fabricating a semiconductor device includes forming an interlayer insulating structure on a substrate, forming a contact hole that penetrates the interlayer insulating structure to expose the substrate, forming an amorphous silicon layer including a first portion and a second portion, the first portion covering a top surface of the substrate exposed by the contact hole, the second portion covering a sidewall of the contact hole, providing hydrogen atoms into the amorphous silicon layer, and crystallizing the first portion using the substrate as a seed.

Abstract: Fabricating high efficiency, high linearity N-polar gallium-nitride (GaN) transistors by selective area regrowth is disclosed. A demand for high efficiency components with highly linear performance characteristics for radio frequency (RF) systems has increased development of GaN transistors and, in particular, aluminum-gallium-nitride (AlGaN)/GaN high electron mobility transistor (HEMT) devices. A method of fabricating a high efficiency, high linearity N-polar HEMT device includes employing a selective area regrowth method for forming a HEMT structure on the Nitrogen-face (N-face) of a GaN buffer, a natural high composition AlGaN/AlN back barrier for carrier confinement, a thick undoped GaN layer on the access areas to eliminate surface dispersion, and a high access area width to channel width ratio for improved linearity. A problem of impurities on the GaN buffer surface prior to regrowth creating a leakage path is avoided by intentional silicon (Si) doping in the HEMT structure.

Abstract: A package includes an Integrated Voltage Regulator (IVR) die, wherein the IVR die includes metal pillars at a top surface of the first IVR die. The package further includes a first encapsulating material encapsulating the first IVR die therein, wherein the first encapsulating material has a top surface coplanar with top surfaces of the metal pillars. A plurality of redistribution lines is over the first encapsulating material and the IVR die. The plurality of redistribution lines is electrically coupled to the metal pillars. A core chip overlaps and is bonded to the plurality of redistribution lines. A second encapsulating material encapsulates the core chip therein, wherein edges of the first encapsulating material and respective edges of the second encapsulating material are vertically aligned to each other. An interposer or a package substrate is underlying and bonded to the IVR die.

Abstract: A semiconductor device includes a first substrate structure including a first substrate, gate electrodes stacked on the first substrate, and extended by different lengths to provide contact regions, cell contact plugs connected to the gate electrodes in the contact regions, and first bonding pads disposed on the cell contact plugs to be electrically connected to the cell contact plugs, respectively, and a second substrate structure, connected to the first substrate structure on the first substrate structure, and including a second substrate, circuit elements disposed on the second substrate, and a second bonding pad bonded to the first bonding pads, wherein, the contact regions include first regions having a first width and second regions, of which at least a portion overlaps the first bonding pads, and which have a second width greater than the first width, and the second width is greater than a width of the first bonding pad.

Abstract: An electronic device includes a semiconductor memory comprising row lines, column lines, memory cells, and a plurality of contact plugs including row contact plugs respectively coupled to the row lines and column contact plugs respectively coupled to the column lines. Each memory cell is coupled to a row line and a column line, and has a current path comprising a portion of that row line and a portion of that column line. First and second contact plug are respectively coupled to first and second memory cells respectively having first and second current paths. A resistance of the first current path is lower than a resistance of the second current path, and a resistance of the first contact plug is increased relative to a resistance of the second contact plug to offset the lower resistance of the first current path.

Abstract: The present disclosure relates to an array substrate, a display panel, and a display device. In an embodiment, an array substrate is provided that comprises: a substrate; and a pixel defining layer disposed on the substrate, the pixel defining layer including a plurality of openings and a partition portion for separating the plurality of openings from each other, wherein the partition portion has a first recess.

Abstract: Embodiments described herein relate to substrate processing methods. The methods include forming a patterned hardmask material on a substrate, forming first mandrel structures on exposed regions of the substrate, and depositing a gap fill material on the substrate over the hardmask material and the first mandrel structures. The first mandrel structures are removed to expose second regions of the substrate and form second mandrel structures comprising the hardmask material and the gap fill material. Fin structures are deposited on the substrate using the second mandrel structures as a mask.

Abstract: Gate fingers (2-1 to 2-6) are arranged in one direction and each of the gate fingers is disposed so as to be adjacent to a corresponding one of drain electrodes (3-1 to 3-3) and a corresponding one of source electrodes (4-1 to 4-4) alternately, and have non-uniform gate head lengths.

Abstract: A light-emitting apparatus package of the present invention includes (i) an electrically insulated ceramic substrate, (ii) a first concave section formed in the direction of thickness of the ceramic substrate so as to form a light exit aperture in a surface of the ceramic substrate, (iii) a second concave section formed within the first concave section in the further direction of thickness of the ceramic substrate so that one or more light-emitting devices are provided therein, (iv) a wiring pattern for supplying electricity, which is provided in the first concave section, and (v) a metalized layer having light-reflectivity, which is (a) provided between the light-emitting device and the surface of the second concave section of the substrate, and (b) electrically insulated from the wiring pattern.

Abstract: The present technology relates to a semiconductor memory device. The semiconductor memory device includes a plurality of channel plugs disposed in a cell region of a semiconductor substrate, a first dummy region disposed at one end portion of the cell region and a second dummy region disposed at an other end portion of the cell region, and first dummy plugs disposed in the first dummy region and second dummy plugs disposed in the second dummy region. The number of the first dummy plugs is different than the number of the second dummy plugs.

Abstract: The present disclosure provides one embodiment of a method of forming an integrated circuit structure. The method includes forming a shallow trench isolation (STI) structure in a semiconductor substrate of a first semiconductor material, thereby defining a plurality of fin-type active regions separated from each other by the STI structure; forming gate stacks on the fin-type active regions; forming an inter-layer dielectric (ILD) layer filling in gaps between the gate stacks; patterning the ILD layer to form a trench between adjacent two of the gate stacks; depositing a first dielectric material layer that is conformal in the trench; filling the trench with a second dielectric material layer; patterning the second dielectric material layer to form a contact opening; and filling a conductive material in the contact opening to form a contact feature.

Abstract: A display apparatus including a substrate; a display area arranged on the substrate and including a plurality of pixels, and a peripheral area arranged outside the display area; a dam surrounding the display area; a crack detector arranged between the dam and an end of the substrate and electrically connected to at least one of the plurality of pixels; a crack prevention dam arranged between the dam and the end of the substrate; and an encapsulation layer including a first inorganic layer, an organic layer, and a second inorganic layer, each covering the display area and a portion of the peripheral area. The first inorganic layer and the second inorganic layer in the encapsulation layer extend to the end of the substrate.

Abstract: A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first metal layer located on the first semiconductor substrate, a second metal layer located on the second semiconductor substrate, a third metal layer, a first alloy layer, and a second alloy layer. The third metal layer extends between the first metal layer and the second metal layer. The first alloy layer comprises components of the first and third metal layers, and is provided between the first metal layer and the third metal layer. The second alloy layer comprises components of the second and third metal layers, and is provided between the second metal layer and the third metal layer. At least one of the first metal the second metal layers projects into the third metal layer at a circumferential edge portion thereof.

Abstract: A novel method, composition and storage and delivery container for using antimony-containing dopant materials are provided. The composition is selected with sufficient vapor pressure to flow at a steady, sufficient and sustained flow rate into an arc chamber as part of an ion implant process. The antimony-containing material is represented by a non-carbon containing chemical formula, thereby reducing or eliminating the introduction of carbon-based deposits into the ion chamber. The composition is stored in a storage and delivery vessel under stable conditions, which includes a moisture-free environment that does not contain trace amounts of moisture. The storage and delivery container is specifically designed to allow delivery of high purity, vapor phase antimony-containing dopant material at a steady, sufficient and sustained flow rate.