Patents Examined by Thomas J. Cleary
  • Patent number: 10019394
    Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.
    Type: Grant
    Filed: March 21, 2017
    Date of Patent: July 10, 2018
    Assignee: ARM Limited
    Inventors: Michael Alexander Kennedy, Anthony Jebson
  • Patent number: 10001826
    Abstract: A method, system, and computer program product for facilitating power instability in a central electronics complex (CEC) of data storage computing environment in advance of a potential power failure is provided. Upon receipt of a first early power off warning (EPOW) signal indicating power instability, a first priority of execution of a first data storage task to be performed pursuant to a new data storage request is decreased, while a second priority of execution of a second data storage task to destage data in nonvolatile storage (NVS) to disk is increased. Upon receipt of a second EPOW signal indicating power failure, a system shutdown procedure is executed.
    Type: Grant
    Filed: January 15, 2009
    Date of Patent: June 19, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Lei Liu
  • Patent number: 9996490
    Abstract: A transmitter is configured to scale up a low bandwidth delivered by a first processing element to match a higher bandwidth associated with an interconnect. A receiver is configured to scale down the high bandwidth delivered by the interconnect to match the lower bandwidth associated with a second processing element. The first processing element and the second processing element may thus communicate with one another across the interconnect via the transmitter and the receiver, respectively, despite the bandwidth mismatch between those processing elements and the interconnect.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: June 12, 2018
    Assignee: NVIDIA Corporation
    Inventors: Marvin A. Denman, Dennis K. Ma, Stephen David Glaser
  • Patent number: 9996492
    Abstract: The invention relates to a method and a coupling device for dynamically allocating USB endpoints of a USB interface, which can be accessed using at least two applications, comprising: a USB interface that has at least two ports, each of which comprises at least one USB endpoint; and a control device for dynamically allocating the USB endpoints. The control device is designed so as to preconfigure each USB endpoint which is required for the at least two applications by means of an initialization process, and thus the control device can switch the allocation of the endpoints according to the access using at least one of the applications without the USB endpoints affected by the switch having to be deactivated.
    Type: Grant
    Filed: April 5, 2017
    Date of Patent: June 12, 2018
    Assignee: Unify GmbH & Co. KG
    Inventors: Elmar Albert, Andras Selmeczi
  • Patent number: 9996491
    Abstract: A network interface device for a host computer includes a network interface, configured to transmit and receive data packets to and from a network. Packet processing logic transfers data to and from the data packets transmitted and received via the network interface by direct memory access (DMA) from and to a system memory of the host computer. A memory controller includes a first memory interface configured to be connected to the system memory and a second memory interface, configured to be connected to a host complex of the host computer. Switching logic alternately couples the first memory interface to the packet processing logic in a DMA configuration and to the second memory interface in a pass-through configuration.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: June 12, 2018
    Assignee: Mellanox Technologies, Ltd.
    Inventors: Diego Crupnicoff, Todd Wilde, Richard Graham, Michael Kagan
  • Patent number: 9984022
    Abstract: Methods and apparatus to identify a communication protocol being used in a process control system are disclosed. An example apparatus includes a process control device including a port to be in communication with a bus, the process control device to receive a first signal at the port and a second signal at the port, the process control device including a protocol detector to compare the first signal to reference communication protocols to identify the first signal as being associated with a first communication protocol, the protocol detector to compare the second signal to the reference communication protocols to identify the second signal as being associated with a second communication protocol, the first communication protocol being different than the second communication protocol, the processor to process the first signal based on the first communication protocol and the second signal based on the second communication protocol.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: May 29, 2018
    Assignee: BRISTOL, INC.
    Inventor: Xuedong Liu
  • Patent number: 9971715
    Abstract: A slave device is realized that establishes a link with a master device or another slave device such that a large link delay hardly occurs. The slave device includes a PHY unit, a COM unit, and a MPU unit. The PHY unit starts an operation according to the specification of the AutoMDI/MDI-X function when the slave device is turned on or the PHY unit itself is reset. After a predetermined time period has elapsed, the MPU unit resets the COM unit, and the PHY unit is reset in response to the reset of the COM unit.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 15, 2018
    Assignee: OMRON Corporation
    Inventors: Hirohito Mizumoto, Yoshimi Niwa, Megumu Asano, Hajime Ujiie, Satoshi Yamawaki
  • Patent number: 9965423
    Abstract: When initializing a card-shaped device inserted in a card interface, operation mode acquiring means incorporated in an electronic device acquires operation mode information, stored in a register file incorporated in the card-shaped device, by a predetermined procedure using a predetermined pin. Operation mode setting means incorporated in the electronic device executes signal assignment on a plurality of data pins peculiar to an operation mode indicated by the acquired operation mode information, thereby switching a data transfer width, and allowing the card-shaped device to operate in the operation mode.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: May 8, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Kosei Okamoto, Hiroyuki Sakamoto, Akihisa Fujimoto, Masao Suga
  • Patent number: 9965406
    Abstract: Delay in establishing communication is suppressed in a network system including a master device and a slave device. Provided is a setting method for performing communication setting for at least one of a master device and a slave device serving as a target device, the method including a storage step of storing a value of a communication parameter in a state in which the target device has established communication, and a setting step of, in communication setting in a preparatory stage for the target device to start communication, setting the value of the communication parameter that was stored in the storage step.
    Type: Grant
    Filed: November 24, 2015
    Date of Patent: May 8, 2018
    Assignee: OMRON Corporation
    Inventors: Hirohito Mizumoto, Satoshi Yamawaki, Kayoko Isogai
  • Patent number: 9965223
    Abstract: Systems and methods for management of scalable storage architectures are disclosed. The system includes one or more storage backplanes, each storage backplane configured to interface with one or more hard disk drives. The system includes a baseboard management controller, which includes an interface to communicate with one or more of the storage backplanes and programmable logic configured to detect the presence of one or more hard disk drives in an interfaced storage backplane and control one or more status indicators, wherein each status indicator is related to at least one of the hard disk drives in the interfaced storage backplane.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: May 8, 2018
    Assignee: Dell Products L.P.
    Inventors: Shawn Joel Dube, Tim Lambert, Surender V. Brahmaroutu
  • Patent number: 9946675
    Abstract: A communication bus system is provided. The communication bus system includes a communication bus having a plurality of isolatable segments and a bus master coupled to a first end of the communication bus. The bus master is configured to couple to a second end of the communication bus and to decouple from the second end of the communication bus based on a selection signal. A method for operating a communication bus is also disclosed.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: April 17, 2018
    Assignee: Atieva, Inc.
    Inventor: Richard J. Biskup
  • Patent number: 9921981
    Abstract: A master device is provided which is coupled to a shared single line interrupt request (IRQ) bus and a control data bus. The master device group slave devices coupled to the shared single line IRQ bus into one or more groups, where each group is associated with a different IRQ signal. The master device then monitors the IRQ bus to ascertain when an IRQ signal is asserted by at least one slave device. The master device then identifies a group to with which the IRQ signal is associated. The slave devices for the identified group are then scanned or queried by the master device to ascertain which slave device asserted the IRQ signal on the IRQ bus. Each group uses a distinguishable IRQ signal to allow the master device to ascertain which group to query or scan.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: March 20, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Shoichiro Sengoku, Richard Dominic Wietfeldt, George Alan Wiley
  • Patent number: 9904637
    Abstract: System, methods and apparatus are described that facilitate transmission of data, particularly between two devices within an electronic apparatus. A method performed by a slave device coupled to a serial bus includes detecting an event related to a function of the slave device, initiating a first counter in the slave device, asserting an in-band interrupt request by driving at least one signal on the serial bus, and transmitting content of the first counter to a bus master coupled to the serial bus during an interrupt handling procedure. The first counter may count cycles of a clock used by the slave device or occurrences of a signaling state or condition on the serial bus. The content of the first counter may be used to determine a time stamp for the event.
    Type: Grant
    Filed: November 23, 2015
    Date of Patent: February 27, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Shoichiro Sengoku
  • Patent number: 9898422
    Abstract: A method of setting by a docking center a direct connection between a dockee and a peripheral device in a wireless docking network is provided. The method includes grouping peripheral devices depending on each service in association with the peripheral devices and performing a setting of authorization for a corresponding group; and providing a docking service to the dockee which joins in the group while supporting a direct connection with at least one of the peripheral devices.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: February 20, 2018
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jong-Hyo Lee, Karthik Srinivasa Gopalan, Kiran Bharadwaj Vedula, Jun-Hyung Kim
  • Patent number: 9880968
    Abstract: Embodiments are directed to a system comprising: a first device, and a second device coupled to the first device via an interface that provides a handshaking algorithm that ensures that only one of the first device and the second device initiates communication over the interface at a given point in time.
    Type: Grant
    Filed: January 20, 2015
    Date of Patent: January 30, 2018
    Assignee: WALTER KIDDE PORTABLE EQUIPMENT INC.
    Inventor: Stanley D. Burnette
  • Patent number: 9875206
    Abstract: Devices and methods for extending USB-compliant communication distances, including USB 3.0 SuperSpeed communication, are provided. In some embodiments, a host is communicatively coupled to a device that provides an upstream facing port, and a USB device is communicatively coupled to a device that provides a downstream facing port. The upstream facing port and downstream facing port are coupled via a communication channel. In some embodiments, the upstream facing port and downstream facing port generate packets to ensure that timing requirements of the USB specification are met regardless of the latency of the communication channel.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: January 23, 2018
    Assignee: Icron Technologies Corporation
    Inventor: Aaron T.J. Hall
  • Patent number: 9846662
    Abstract: A chained Command/Push/Pull (CPP) bus command is output by a first device and is sent from a CPP bus master interface across a set of command conductors of a CPP bus to a second device. The chained CPP command includes a reference value. The second device decodes the command, in response determines a plurality of CPP commands, and outputs the plurality of CPP commands onto the CPP bus. The second device detects when the plurality of CPP commands have been completed, and in response returns the reference value back to the CPP bus master interface of the first device via a set of data conductors of the CPP bus. The reference value indicates to the first device that an overall operation of the chained CPP command has been completed.
    Type: Grant
    Filed: September 20, 2014
    Date of Patent: December 19, 2017
    Assignee: Netronome Systems, Inc.
    Inventors: Salma Mirza, Gavin J. Stark
  • Patent number: 9824049
    Abstract: Methods and systems are provided routing access requests produced by a function to a physical sharing machine on a computer interconnect fabric. Access requests are routed through a switch that includes an NTB, the NTB using an address-lookup table to ensure that access requests made by multiple physical sharing machines are appropriately isolated from one another.
    Type: Grant
    Filed: November 19, 2015
    Date of Patent: November 21, 2017
    Assignee: Google Inc.
    Inventor: Benjamin C. Serebrin
  • Patent number: 9817774
    Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes N machines configured to handle requests from the requesting interconnect and for handling allocated responses from the serving interconnect, wherein each of the N machines has an allocated local count; a tracking entity configured to track priorities of the N machines for issuing received requests to the serving interconnect and for issuing received responses to the requesting interconnect based on the N local counts; a first arbiter configured to arbitrate the received requests to be issued to the serving interconnect based on the tracked priorities; and a second arbiter configured to arbitrate the received responses to be issued to the requesting interconnect based on the tracked priorities.
    Type: Grant
    Filed: June 19, 2015
    Date of Patent: November 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Florian A. Auernhammer, Joseph G. McDonald
  • Patent number: 9811481
    Abstract: Certain aspects direct a distributed Intelligent Platform Management Interface (D-IPMI) system. The system includes a computing device and a distributed management device. The distributed management device includes a first management device and at least one second management device physically separated from each other. A stack interface connects the first management device and the second management device to perform an internal communication between the first management device and the second management device. The first management device may be used to perform time critical functions related to the computing device, and the second management device may be used to perform non-critical functions. For example, the first management device may perform system power control of the computing device, monitor system components and obtaining system information of the computing device, and perform system communication with the computing device.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: November 7, 2017
    Assignee: AMERICAN MEGATRENDS, INC.
    Inventors: Anurag Bhatia, Sanjoy Maity