Abstract: A method for control of latency information through logical block addressing is described comprising receiving a computer command, performing a read flow operation on a computer buffer memory based on the computer command; populating at least one metadata frame with data based on logical block address latency information; initiating a serial attached data path transfer for one of transmitting and receiving data to the computer drive and transmitting data to a host based on the second latency.

Abstract: An Embedded Universal Serial Bus 2.0 (USB2) device includes a physical layer having a detection mechanism to detect an Single-ended 1 (SE1) valid state and differentiate the SE1 valid state from other USB2 states.

Abstract: A computer system includes a system bus having multiple lanes, one or more peripheral devices, and a bus controller. The peripheral devices are coupled to the system bus. The bus controller is configured to receive, from one or more of the peripheral devices, respective indications of numbers of the lanes requested by the peripheral devices, and to configure the system bus in response to the indications.

Abstract: Example implementations relate to an arbitration node. For example, an arbitration node can include instructions to receive, at the arbitration node at a level of a binary tree structure, a first request including a first request signal and a first priority signal and receive a second request including a second request signal and a second priority signal. In some examples, the arbitration node can include instructions to determine priority of requests by comparing the first request signal and the second request signal and by comparing the first priority signal and the second priority, and send a request signal and a priority signal of the request with the determined priority to a subsequent arbitration node at a subsequent level of the binary tree structure.

Abstract: A data diode provides a flexible device for collecting data from a data source and transmitting the data to a data destination using one-way data transmission. On-board processing elements allow the data diode to identify automatically the type of connectivity provided to the data diode and configure the data diode to handle the identified type of connectivity.

Abstract: Example methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to verify interconnection between media devices and device meters with touch sensing integrated circuits are disclosed. Example methods disclosed herein include accessing an output of a touch sensing integrated circuit associated with a meter, the touch sensing integrated circuit to electrically couple with an interface of a media device monitored by the meter. Example methods disclosed herein also include determining the meter is coupled to the media device via the interface in response to the output of the touch sensing integrated circuit.

Abstract: Systems and methods for enabling wellsite data transfer between petroleum field devices using coded data images, such as matrix barcodes, are provided. Wellsite data is obtained in a first format at a first computing device. The wellsite data is converted from the first format into a second format to be used for matrix barcode generation. At least one matrix barcode is generated based on the converted wellsite data. A representation of the generated matrix barcode is presented via an output device of the first computing device for transfer to a second computing device.

Abstract: There are disclosed various methods and apparatuses for a device setup. In some embodiments of the method a signal from a peripheral device is detected by an apparatus and biometric data is received from the peripheral device. The biometric data is transmitted to a server. An indication whether the server has found biometric identification corresponding to the biometric data or other information indicative of that the apparatus and the peripheral device are attached to a same user is received from the server. If the indication reveals that the server has found biometric identification corresponding to the biometric data or other information indicative of that the apparatus and the peripheral device are attached to a same user configuration data is received from the server and used for configuring at least one of the apparatus and the peripheral device. In some embodiments the apparatus comprises means for implementing the method.

Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.

Abstract: In accordance with embodiments of the present disclosure, an information handling system may include two processor sockets comprising a first processor socket and a second processor socket, a first information handling resource communicatively coupled to the first processor socket, second information handling resource, and a bus exchange switch communicatively coupled to the first processor socket, the second processor socket, and the second information handling resource such that: if the second processor socket is unpopulated, the bus exchange switch creates a first electrically conductive path between the first processor socket and the second information handling resource, and if the second processor socket is populated, the bus exchange switch creates a second electrically conductive path between the first processor socket and the second processor socket and creates a third electrically conductive path between the second processor socket and the second information handling resource.

Abstract: An autonomous circular buffer is described in connection with the various embodiments of the present disclosure. An autonomous circular buffer controller may control movement of data between a user of the autonomous circular buffer and a peripheral. The autonomous circular buffer may enable direct memory access type data movement, including between the user and the peripheral.

Abstract: When a data request is sent from a master device in master-slave communication, a slave device determines whether a piece of data requested by the data request among data stored on the slave device side has been updated after previous transmission of the piece of data. If the piece of data has been updated, the slave device sends the updated piece of data as a response to the data request. If the piece of data has not been updated, the slave device suspends a response to the data request. Thus, a communication system is built which can reduce network processing load and the volume of communication data in the case where the master device periodically acquires data from the slave device.

Abstract: A system for passive device identification includes a passive device communicatively coupled to a processing device. The processing device includes a passive device identifier configured to a current supplied to the passive electronic device at discrete intervals and to sample a voltage of the passive electronic device at each one of the discrete intervals to generate a dataset of current-voltage pairs. The passive define identifier is further configured to identify the passive electronic device based on the generated dataset.

Abstract: An electronic device and method are disclosed herein. The electronic device may include a housing, a socket disposed in the housing, a tray insertable into the socket, and into which at least one of a storage medium card and a subscriber identity module (SIM) card is insertable, a communication circuit disposed in the housing, a processor disposed in the housing and electrically coupled to the communication circuit and a memory electrically coupled to the processor.

Abstract: A method for sensing cable insertion into a connection installed in an electronic device. The electronic device includes a connector for inserting a cable, a first power manager configured to, when power is provided from the cable, output a signal corresponding to the power, a second power manager configured to transmit information instructing a supplying of the power to a processor, in accordance with the output of the signal, and the processor configured to control opening a path for the cable in accordance with the information.

Abstract: An apparatus is provided which comprises: an input/output (I/O) port; an adaptor; a physical layer to interface between the I/O port and the adaptor; a first controller associated with a first type of communication; and a second controller associated with a second type of communication, wherein the adaptor is to selectively couple the I/O port, via the physical layer, to one of the first controller or the second controller, based at least in part on a type of device coupled to the I/O port.

Abstract: A data storage system, including a host server having storage processors, a PCIe fabric, and a GBE fabric, and two or more data storage modules having a bank of DRAM, long-term storage drives, a host interface, including a PCIe interface and a GBE interface, an application specific integrated circuit connected to the host interface, the storage drives, and the DRAM, and a battery, the battery providing power to the DRAM and SSDs in an event of failure of a main power supply. Data streams transmitted from the host server via a PCIe connection of the PCIe fabric are received at the host interface and placed directly in DRAM as a write-back cache operation. In addition, the battery provides the DRAM with non-volatile memory capabilities and the storage modules with portability. A method for arbitration of write requests between the storage processors of the data storage system is also disclosed.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: A method of controlling a mode of a device is provided. The method includes determining a Vbus voltage on a Vbus pin in a USB connector on the device, comparing the Vbus voltage with a threshold, and configuring the device based on the comparison of the Vbus voltage and the threshold.