Abstract: The invention provides methods and apparatus for the reading of data from digital memory devices, and methods and apparatus for the wireless transmittal of the data to computing devices. The apparatus combines hardware and software to serve files from the memory device to any web-capable computing device, such as a portable computer, tablet, or smart phone, by creating HTML wrappers around the files and directories on the memory device. The data is presented to the computing devices in a secure manner, through the agency of a web browser running on each device.

Abstract: Embodiments herein use a single buffer that comprises a plurality of serially connected data cells to serially store data attributes and the respective data source identifiers from incoming data requests such that each stored data source identifier is used to match with a response message that corresponds to a respective data request. When a response message is received at the data interface, the data interface searches among the previously stored data attributes at the single buffer and selectively outputs a previously stored data attribute that corresponds to a data request to match with the response message. The data interface then uses information from the previously stored data attribute to route the response message to the data source that originates the data request.

Abstract: An access control method includes: determining a number of a plurality of commands to be continuously transferred; transferring to a storage device, a transfer preparation completion command indicating that preparation for transfer of the plurality of commands is completed, when it is determined that the number is greater than or equal to a threshold value; transferring, in sequence, to the storage device, the plurality of commands when it is determined that the number is less than the threshold value; when a command transferred from the host device is the transfer preparation completion command, issuing a direct memory access request to the host device based on the transfer preparation completion command and receiving the plurality of commands transferred from the host device by a direct memory access method based on the direct memory access request; and accessing the storage, based on each of the plurality of commands received.

Abstract: Described is an apparatus which comprises: a first electrical path comprising at least one driver and receiver; and a second electrical path comprising at least one driver and receiver, wherein the first and second electrical paths are to receive a same input signal, wherein the first electrical path and the second electrical path are parallel to one another and have substantially the same propagation delays, and wherein the second electrical path is enabled during a first operation mode and disabled during a second operation mode.

Abstract: An apparatus (301) for communication according to a Universal Serial Bus, USB, specification, comprising: a first USB device (301) and a second USB device (306) for connecting operatively to a first USB host and a second USB host, respectively; an audio interface stage (320) configured to interface with an audio component such as a headset; and audio controller (316). The audio controller (316) is configured with: a first channel (327), channeling audio signals between the first USB device and the audio interface stage (320), and a second channel (328), channeling audio signals between the second USB device and the audio interface stage (320); wherein the audio controller (316) automatically switches between the first channel (327) and the second channel (328) while giving priority to audio signals on the first channel over audio signals on the second channel.

Abstract: An interrupt interface of a central processing unit (CPU) comprises a bus with a plurality of interfaces to various components of the CPU. These components can include a memory that includes instructions to execute operations of a processor component, a plurality of virtual machines (VMs) and a virtual machine monitor (VMM)/hypervisor configured to execute the plurality of VMs. The processor can receive interrupt requests (interrupt) as service requests in parallel, which can be executed by the VMM or any one or more of the plurality of VMs to execute VM applications on a dedicated instance of a guest operating system for a task. The processor can further determine whether to grant an interrupt request to the VMM and the VMs based on predetermined criteria, including a current task priority, a pending interrupt priority, or an interrupt enable, associated with the current status of each of the component.

Abstract: A write-enable circuit outputting a write-enable signal for digital data, in an analog-to-digital converter comprising a bus-controller connected to an external unit, an arithmetic processing unit performing data processing, and an arithmetic unit holding the data and having a normal access mode in which the data are temporarily written into the arithmetic processing unit and then written into the bus-controller and a high-speed access mode in which the data are written directly into the bus-controller. The circuit comprises an address-coincidence-determining circuit provided in the arithmetic unit outputting a write-enable signal from the arithmetic unit when a predetermined address for a memory of the bus-controller coincides with an address specified by the arithmetic processing unit; and a logic circuit inputting the write-enable signal to the bus-controller when the arithmetic processing unit asserts a high-speed access signal indicating that now is in the high-speed access mode.

Abstract: Provided is a time-shift retransmission system which is a system that manages communication of a remote sensor connected to a communication line, the time-shift retransmission system including: a) temporary storage means in which measurement values measured according to a sampling schedule by the remote sensor is temporarily stored at a predetermined interval; and b) retransmission means that retransmits the measurement values according to a retransmission schedule with plural different cycles, in which a delay time from the measurement to the retransmission differs according to the cycle, and the delay time is set in a range in which the data amount of a measurement value group that is temporarily stored within the delay time falls within the storage capacity of the temporary storage means.

Abstract: An optical transceiver that shortens an elapsed time for loading data from an external device, and a method of loading data are disclosed. The optical transceiver includes an inner memory, a central processing unit (CPU), and a serial communication line connecting the CPU with the external device. The CPU actively loads data stored in the external device into the inner memory through the serial communication line by operating as a master device in the serial communication line.

Abstract: A memory system includes a storage device and a host device. The storage device includes a memory device and a device controller. The device controller is configured to store device information. The device information includes a level of a power supply voltage required for the memory device. The host device includes a host controller and a power management integrated circuit (PMIC). The host device is configured to send a query command to receive the device information from the device controller during a power setting period. The PMIC is configured to supply a first level of power supply voltage to the memory device during the power setting period and, after the power setting period, selectively supply one of the first level of power supply voltage and a second level of power supply voltage to the memory device. The first level of power supply voltage is lower than the second level of power supply voltage.

Abstract: Disclosed is a method by a docking center of assisting communication between a dockee and a peripheral device to which the docking center is connected, including transmitting, as a group owner of a first group, to the dockee, information for a direct connection between the dockee and the peripheral device, receiving an assist request for setting the direct connection based on the information, transmitting a response indicating whether the assist request is accepted, receiving a release request for releasing a connections between the dockee and the docking center and between the docking center and the peripheral device, terminating control of the peripheral device, receiving a joining request for requesting to join a second group, transmitting a response for joining the second group as a client, the dockee being set as a second group owner, and operating as the group owner of the first group and the client of the second group.

Abstract: Aspects of the present invention include a method, system and computer program product that implements a memory management scheme for each processor in a multiprocessor system. The method includes pre-allocating, for each processor in a multiprocessor system, a set of memory buffers; and implementing a metadata bitmap for each pre-allocated set of memory buffers, wherein the metadata bitmap for each pre-allocated set of memory buffers comprises a plurality of bits, and wherein each of the plurality of bits is indicative of a usage state of a corresponding one of the memory buffers within each pre-allocated set of memory buffers.

Abstract: One embodiment relates to a method of transferring configuration information for a connected object wherein the method is performed by a terminal. The method may comprise detecting a connection of a mass memory on a peripheral connector of the terminal, associating the detected mass memory with at least one item of configuration information for the connected object, obtaining the at least one item of configuration information, and transferring the at least one item of configuration information to the mass memory.

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

Abstract: Aspects of the present invention include a method, system and computer program product that implements a memory management scheme for each processor in a multiprocessor system. The method includes pre-allocating, for each processor in a multiprocessor system, a set of memory buffers; and implementing a metadata bitmap for each pre-allocated set of memory buffers, wherein the metadata bitmap for each pre-allocated set of memory buffers comprises a plurality of bits, and wherein each of the plurality of bits is indicative of a usage state of a corresponding one of the memory buffers within each pre-allocated set of memory buffers.

Abstract: An electronic device is provided. The electronic device includes a transceiver that communicates with an external electronic device and at least one processor electrically connected with the transceiver. The processor is configured to obtain context information about an operation being performed at the electronic device, to generate identification information about a recommended operation associated with the operation being performed, based on the context information about the operation being performed and to send the identification information about the recommended operation to the external electronic device by using the transceiver.

Abstract: A printing apparatus operating in a service mode is reactivated when the printing apparatus receives a reactivation instruction from an external device connected to the printing apparatus by a direct wireless communication function. The reactivated printing apparatus starts an operation in the service mode instead of a normal operation mode.

Abstract: An information processing system, device and method wherein a base board is configured to couple to both back and midplane systems as well as optical modules for use in a data center rack system. Specifically, a base board adapter is configured to electrically couple to an integrated backplane/midplane electronic interface of the base board and translate the signals to one or more optical interface module connectors such that one or more optical interface modules are able to be coupled to the base board.

Abstract: Performing transactions on a bus by first generating a sequence of commands by an initiator module and queuing the sequence of commands in a queue module. A first one of the sequence of commands is sent from the queue module via the bus to a target module. The queue module is paused while waiting for a response via the bus from the target module; however, the initiator may continue processing another task. The queue module repeatedly sends a next command via the bus to the target module and waits for a response via the bus from the target module until a last one of the sequence of commands is sent to the target module. The queue module provides only a single acknowledgement to the initiator module after the sequence of commands has been transferred to the target module.

Abstract: Methods and systems are provided routing access requests produced by a function to a physical sharing machine on a computer interconnect fabric. Access requests are routed through a switch that includes an NTB, the NTB using an address-lookup table to ensure that access requests made by multiple physical sharing machines are appropriately isolated from one another.