Abstract: A multi-processor system includes a first processor; a second processor; a common memory configured to store data generated by the first processor and data generated by the second processor; and a memory interface circuit configured to interface between the common memory and the first and second processors, the first processor being configured to demodulate and decode a signal received through wireless communication, and store the decoded data in the common memory via the memory interface circuit, the memory interface circuit being configured to read and decipher the decoded data stored in the common memory, and store the deciphered data in the common memory.

Abstract: A selectively transparent bridge facilitates a PCI device presenting itself to the host as a PCI-to-PCI bridge but selectively hiding and isolating hardware from the host bus. PCI configuration may be achieved through the standard PCI Express configuration mechanisms, but instead of configuring devices directly, a configuration processor in the selectively transparent bridge may intercept the configuration packets from the host, and create a virtual configuration to alter how the bus topology appears to the host. Devices are selectively hidden and managed by the configuration processor, resulting in simplified complexity and bus depth. Since the selectively transparent bridge appears to the host as a transparent bridge, no special drivers or resource preallocations are required, although the selectively transparent bridge fully supports special drivers and/or resource preallocations. Devices located/connected downstream of the bridge may therefore function with unmodified drivers.

Abstract: An object is to make it possible to add a vendor-unique command at the time at which addition of a vendor-unique command becomes necessary later even in the case where the device side does not have a dedicate pin for updating in communication control based on a SATA standard. An information processing system that performs data communication between a host and a device in conformity with the SATA standard, and the host transmits a setup command to which information on an undefined command is written to the device, and the device: has a command table for commands in conformity with the SATA standard, in which a command code to identify each command and information on a transfer protocol of each command are described; and makes the undefined command available between the host and the device by writing information on the undefined command to the command table in accordance with the received setup command.

Abstract: An information handling system (IHS), peripheral component interface (PCI) system and method for expanding PCI nodes in an IHS. The PCI system includes a primary PCI node. The primary PCI node has a PCI switch communicatively coupled to a processor via a system interconnect. The PCI switch is communicatively coupled to several PCI devices. A communication module is communicatively coupled to the PCI switch. A PCI expansion node is communicatively coupled to the primary PCI node via a PCI bus and a sideband bus. The IHS executes firmware that enables expansion of the IHS by configuring the primary PCI node to recognize the one or more interconnected PCI expansion nodes and integrate the functions of the interconnected PCI expansion nodes into an expanded PCI subsystem. The primary PCI node and PCI expansion node can be substantially identical IHSs, having the same motherboards and chassis.

Abstract: A computer-implemented method for synchronous input/output (I/O) cache line padding is described. The cache line padding occurs between a server having a processor executing an operating system and a recipient control unit. The method can include receiving, via the processor at the recipient control unit, a partial line direct memory access (DMA) write request; fetching, via the processor, a device table entry (DTE) associated with the partial line DMA write request; determining, via the processor, a cache line size for a synchronous input/output (I/O) cache line; and writing a full cache line DMA write request by padding, via the processor, the partial line DMA write request with a padded portion, where the padded portion is based on the cache line size.

Abstract: A method for building a configuration signature for an input/output (I/O) device is described herein. The configuration signature is built based on descriptors of an I/O device and save to a host after an initial connection. After the initial connection, the I/O device may be subjected to modifications. To determine if such modifications exist, the descriptors of the I/O device are compared to the configuration signature after the initial connection.

Abstract: A system, such as a System-on-Chip includes an interface component or PLUG which generates transactions over an IP block, such as an interconnect serving one or more clients via virtual channels. The client or clients are mapped onto the virtual channels via client/virtual channel mappings. The virtual channels are provided as a first set of virtual channels in the interface component which cooperate with a second set of virtual channels in the IP block. First and second client/virtual channel mappings for the first set of virtual channels and the second set of virtual channels are provided. The first and second client/virtual channel mappings are separately programmable and mutually decoupled from one another.

Abstract: A direct memory access control device for at least one computing unit includes a terminal for connecting the direct memory access control device to a bus system that connects the computing unit to a working memory, and processing circuitry configured to read out, from a source module connected to the bus system, first data of at least one information block stored at least temporarily in the source module, ascertain a target address in the working memory for the at least one information block as a function of the first data and of configuration information, and transmit the at least one information block from the source module to the target address using a direct memory access by the source module to the working memory.

Abstract: A remote secure drive access method includes receiving a first message from a second server. The message may be received by a baseboard management controller (BMC) of the first server via a PCIe switch from a second server coupled to the first server via an ExpEther connection. A payload of the message may include identification information identifying the second server. The first server may send an endpoint discover message and receive endpoint device information indicative of peripheral and/or endpoint resources of the second server, including a storage controller associated with a secure drive. Secure drive key information may be obtained from the payload of the first virtual message and sent to the second server to access the secure drive. The exchanged messages may comprise proprietary PCIe transaction layer packets enclosed within an Ethernet packet that includes an ExpEther frame within an Ethernet frame.

Abstract: Various techniques for enabling the control and monitoring of a USB device mode controller to a USB-C connector, for the performance of a USB device mode data connection, are disclosed herein. In an example, a computing system that includes multiple USB-C connectors but a single USB device mode controller may manage the mapping of the controller to a particular connector, through operations that identify the mapping and the characteristics of the connector, process a request to change the mapping of the device mode controller, and perform the change to the mapping of the device mode controller. Such a change may include a disconnection or reassignment of a particular USB-C connector to the controller. Further examples to determine the availability of a USB device mode controller, and respond to a scenario where the USB device mode controller is not available, are also disclosed.

Abstract: A bridge for coupling a requesting interconnect and a serving interconnect connected to a number of coherent units in a computer system includes N machines configured to handle requests from the requesting interconnect and for handling allocated responses from the serving interconnect, wherein each of the N machines has an allocated local count; a tracking entity configured to track priorities of the N machines for issuing received requests to the serving interconnect and for issuing received responses to the requesting interconnect based on the N local counts; a first arbiter configured to arbitrate the received requests to be issued to the serving interconnect based on the tracked priorities; and a second arbiter configured to arbitrate the received responses to be issued to the requesting interconnect based on the tracked priorities.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.

Abstract: A method for extending the range of isochronous USB data transfer, by providing a local extender and a remote extender, coupled respectively to the USB host and the USB device, and coupled to each other via a non-USB cable. After receiving a first In-token from the host, the local extender transmits a first data packet to the host, which contains a data payload having a non-zero length; the data is either generated by the first extender, or previously received from the USB device and stored in a buffer. The local extender forwards the first In-token to the USB device via the remote extender; in response, the USB device generates a second data packet containing requested data and transmits it to the local extender via the remote extender. The local extender stores the second data packet and transmits it to the host in response to a second In-token from the host.

Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

Abstract: A communication device is provided. The communication device includes a master interface unit that is configured to provide an interface between a processor and a register device of the communication device, a slave interface unit that is configured to provide an interface between a hardware block and the register device, a first register that is configured to store real time processed data using the master interface unit, the first register being in operable bilateral communication with the slave interface unit, and a second register that is configured to store real time processed data using the master interface unit, the second register being in operable unilateral communication with the slave interface unit.

Abstract: A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

Abstract: A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus. A module is configured to send a message over the communication bus.

Abstract: Methods, systems, and computer-readable storage media for identifying randomly ordered write commands by a storage device enabled to communicate with a drive compatible with a storage protocol enabling command execution in random order. The storage device may determined a particular order of the identified write commands. The write commands in the determined particular order may be arranged by the storage device. The storage device may send the ordered write commands to the drive. The ordered write commands may allow for pre-fetching of data associated with the write commands by the drive.

Abstract: A data processing apparatus has a plurality of processors and a plurality of interrupt interfaces each for handling interrupt requests from a corresponding processor. An interrupt distributor controls routing of interrupt requests to the interrupt interfaces. A shared interrupt request is serviceable by multiple processors. In response to the shared interrupt request, a target interrupt interface issues an interrupt ownership request to the interrupt distributor, without passing the shared interrupt request to the corresponding processor, if it estimates that the corresponding processor is available for servicing the shared interrupt request. The shared interrupt request is passed to the corresponding processor when an ownership confirmation is received from the interrupt distributor indicating that the processor has been selected for servicing the shared interrupt request.