Abstract: Methods and systems are provided routing access requests produced by a function to a physical sharing machine on a computer interconnect fabric. Access requests are routed through a switch that includes an NTB, the NTB using an address-lookup table to ensure that access requests made by multiple physical sharing machines are appropriately isolated from one another.

Abstract: Fast invalidation in peripheral component interconnect (PCI) express (PCIe) address translation services (ATS) initially utilize a fast invalidation request to alert endpoints that an address is being invalidated with a fast invalidation synchronization command that causes the endpoints to flush through any residual read/write commands associated with any invalidated address and delete any associated address entries in an address translation cache (ATC). Each endpoint may send a synchronization complete acknowledgement to the host. Further, a tag having an incrementing identifier for each invalidation request may be used to determine if an endpoint has missed an invalidation request.

Abstract: A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus. A module is configured to send a message over the communication bus.

Abstract: A system and method of operation of a device programming system includes a protocol emulation layer for translating data storage commands from an initial protocol to the protocol of the programmable devices. The protocol emulation layer simplifies the data access and control of the programmable devices by allowing the reuse of existing code bases for legacy devices.

Abstract: Various examples provide a method and apparatus of generating a system port identity. According to the method, a member device may determine a value c which is the number of unit IDs to be allocated to a chip in an interface board of the member device, c is larger than 1; generate a system port identity which identifies a port in the stack for each of plural first ports of the chip using a first unit ID of the c unit IDs; generate a system port identity for each of plural second ports of the chip other than the first ports using a second unit ID of the c unit IDs.

Abstract: In a power supply system, when a power supply is inserted into a power interface of the OTG peripheral, the power supply supplies power to a USB secondary device connected to a second USB interface of the OTG peripheral; and when the power supply is inserted into the power interface of the OTG peripheral, the OTG peripheral outputs a high-level pulse by using the first USB interface of the OTG peripheral, so as to trigger a terminal connected to the first USB interface to stop supplying power to the USB secondary device; and in addition, the OTG peripheral enables, after a delay of a preset safe time, the power supply to supply power to the terminal connected to the first USB interface.

Abstract: Embodiments are directed to apparatuses and methods involving communication between a first circuit and a second circuit over a wired-data bus. An example apparatus includes an integrated circuit (IC) chip within one of the first and second circuits and a logic circuit. The IC has a first data-communication port and a second data-communication for connection to respective first and second conductors of the wired-data bus. The logic circuit communicates a code multi-bit word out of a set of code multi-bit words over the wired-data bus by using signal transitions communicated on the first and second conductors. The code multi-bit word conveys clocked data bits indicated by the signal transitions, and information unique relative to other ones of the set of code multi-bit words by a known sequential pattern of the signal transitions defined relative to timing associated with the clocked data bits.

Abstract: A data-transmission-format conversion circuit has a first data transmission interface, a second data transmission interface, and a control circuit. The control circuit is coupled to the first data transmission interface and the second data transmission interface for processing data-format conversions between the first data transmission interface and the second data transmission interface. The control circuit is further used to control the second data transmission interface to switch from a first corresponding power mode to a second corresponding power mode when the first data transmission interface is switched from a first power mode to a second power mode. The control circuit is further used to control the second data transmission interface to switch from the first corresponding power mode to a third corresponding power mode when the first data transmission interface is switched from the first power mode to a third power mode.

Abstract: Provided is a communication control system in which a control device and one or a plurality of control target devices are connected through a network, wherein at least one of the plurality of control target devices includes a sub master and a sub slave to be synchronously controlled with each other, and the control device includes a storage unit storing each pieces of information on a synchronization period for synchronizing with the control target device, communication periods, and mutual communication control information for mutually communicate in a mutual communication period shorter than the synchronization period, a calculation unit calculating a control command for commanding an operation in synchronization with the control target device for each control target device, and a communication control unit transmitting the control command including the mutual communication control information to the sub master and the sub slave of the at least one control target device.

Abstract: Various techniques for enabling the control and monitoring of a USB device mode controller to a USB-C connector, for the performance of a USB device mode data connection, are disclosed herein. In an example, a computing system that includes multiple USB-C connectors but a single USB device mode controller may manage the availability of the controller to a particular connector. The computing system may determine availability of a USB device mode controller to control the first USB-C connector, wherein the attempted data connection occurs with the first USB-C connector configured as an upstream facing port. The computing system may further perform, in response, a data role swap of the first USB-C connector to configure the first USB-C connector as a downstream facing port. The computing system may, further continue the attempted data connection with the remote computing system via the first USB-C connector configured as a downstream facing port.

Abstract: Embodiments of systems and methods for providing video redirection across multiple Information Handling Systems (IHSs) are discussed. In some embodiments, a method may include: receiving, via a video redirection client, a video stream produced by a video redirection server executed by a Baseboard Management Controller (BMC) of a selected IHS; providing the video stream to a framebuffer driver, where the frame buffer driver is configured to: (i) store frame data from the video stream onto a framebuffer memory; and (ii) in response to a determination that a host is not available, transmit control signals to a graphics core via an Advanced Microcontroller Bus Architecture (AMBA) high-performance bus (AHB)-to-Peripheral Component Interconnect (PCI) (AHB-to-PCI) bridge, where the graphics core is accessible via a PCI bus exclusively when the host is available; and transmitting the frame data to a display coupled to the chassis.

Abstract: An Integrated Circuit (IC) includes two or more subsystem circuits, a multiplexed bus, a multiplexer/de-multiplexer (MUX/DEMUX) and a logic circuit. The subsystems are independent of one another and are configured to communicate data over multiple General-Purpose Input-Output (GPIO) ports. The multiplexed bus is configured to communicate with circuitry external to the IC. The MUX/DEMUX is configured to translate between the data communicated by the subsystem circuits over the multiple GPIO ports and the multiplexed bus. The logic circuit is independent of the subsystem circuits and is configured to allocate resources of the MUX/DEMUX among the subsystem circuits in response to requests received from the subsystem circuits, and to configure the MUX/DEMUX to provide the allocated resources to the subsystem circuits.

Abstract: Improved power control techniques for integrated peripheral component interconnect express (PCIe) controllers are described. In one embodiment, for example, a processor circuit may comprise an integrated PCIe controller and logic to detect a power reduction trigger, disable the integrated PCIe controller, and remove power from the integrated PCIe controller based on a power removal setting for the integrated PCIe controller. Other embodiments are described and claimed.

Abstract: Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently.

Abstract: An aspect of performance improvement for an active-active distributed non-ALUA (asymmetrical logical unit assignment) system with address ownerships includes receiving an input/output (IO) by a host computer; accessing, by the host computer, an address-to-compute module (a?c) table; and determining, from the table, a target location of the IO request. The target location specifies an address. An aspect further includes determining an address owner of a storage controller port of a storage controller that owns the address of the IO, selecting a path associated with the address owner, and transmitting the IO request to the storage controller port.

Abstract: WebUSB access can be managed for local and redirected USB devices. To enable WebUSB access to a redirected USB device, the server-side agent can force the Winusb.sys function driver to be loaded on the device stack of the USB device by modifying the device's descriptors that are reported during enumeration. To enable WebUSB access to a local USB device, a hook driver can perform similar modifications during enumeration to thereby force the Winusb.sys function driver to be loaded as the function driver on the device stack. The agent or hook driver can also block WebUSB access to a USB device by removing the WebUSB platform capability descriptor during enumeration and/or by blocking requests to access the USB device that originate from a browser process.

Abstract: An embodiment of an extensible memory hub may include one or more upstream interface ports to couple the extensible memory hub to the controller, one or more downstream interface ports to couple the extensible memory hub to one or more of the nonvolatile memory and another extensible memory hub, and a clock circuit to provide a first clock signal at a first frequency to the one or more upstream interface ports and a second clock signal at a second frequency to the one or more downstream interface ports, where the first frequency may be different from the second frequency. Other embodiments are disclosed and claimed.

Abstract: A multi-processor system includes a first processor; a second processor; a common memory configured to store data generated by the first processor and data generated by the second processor; and a memory interface circuit configured to interface between the common memory and the first and second processors, the first processor being configured to demodulate and decode a signal received through wireless communication, and store the decoded data in the common memory via the memory interface circuit, the memory interface circuit being configured to read and decipher the decoded data stored in the common memory, and store the deciphered data in the common memory.

Abstract: A data storage device carrier system includes a carrier configured to support one or more data storage devices, a backplane, including one or more coupling connector devices configured to electrically couple with a motherboard, and an interposer board operable to couple a plurality of the data storage devices supported by the carrier with the backplane. In an embodiment, the one or more coupling connector devices are operable to transfer communication signals and electrical power. The interposer board is operable to provide the electrical power from a single port on the backplane to each of the plurality of the data storage devices. The interposer board is also operable to pass communication signals between a primary port on the backplane to a first one of the plurality of the data storage devices, and to pass communication signals between a secondary port on the backplane to a second one of the plurality of the data storage devices.

Abstract: A data diode provides a flexible device for collecting data from a data source and transmitting the data to a data destination using one-way data transmission. On-board processing elements allow the data diode to identify automatically the type of connectivity provided to the data diode and configure the data diode to handle the identified type of connectivity. Either or both of the inbound and outbound side of the data diode may comprise one or both of wired and wireless communication interfaces.