Abstract: In an example, a biometric sensor, includes a first communication interface to receive information associated with an enumeration of the biometric sensor from a host, a second communication interface, and input sensing circuitry to detect an input signal at the biometric sensor. The biometric sensor further includes a controller to, in response to detecting the input signal, transmit a message to wake up the host via the second communication interface, and in response to receiving an indication that a lid of the host has closed, control operation of the biometric sensor by placing the biometric sensor in a low power state.

Abstract: A video display apparatus includes a power source that supplies first electric power and supplies second electric power that is different from the first electric power to an external device, a current detector that detects a current value when the second electric power is supplied to the external device, an electric power supply controller that includes a plurality of electric power supply modes and performs control that supplies electric power corresponding to one electric power supply mode among the plurality of electric power supply modes to the external device as the second electric power, and a controller that performs control that limits the first electric power when the current value detected by the current detector reaches a predetermined first threshold value.

Abstract: An Uninterrupted Power Supply (UPS) is provided. The UPS comprises Alternating Current (AC) power ports, communication ports, a battery to supply Direct Current (DC) power, a display, a surge controller, a wireless transceiver, a processor, and a non-transitory computer-readable storage medium having executable instructions. The executable instructions when executed by the processor gathers coarse-grain and fine-grain power consumption metrics for a terminal plugged into an AC power port and the battery. The metrics displayed on the display and provided to user-operated devices over the wireless transceiver. User-operated devices include user interfaces that customer configure the executable instructions of the UPS for custom gathering of the metrics, custom aggregation of the metrics, custom reporting the metrics, and custom displaying of the metrics on the display.

Abstract: An image processing chip includes a first interface port, a second interface port, a first upstream facing port (UFP) physical layer module, a first configuration channel detection module, a second upstream facing port (UFP) physical layer module, a second configuration channel detection module, a display signal processing module, a USB signal processing module, an image signal output port and a USB signal output port. The first configuration channel detection module is coupled to the first interface port through a first configuration channel pair, and configured to, after being communicated through a USB specification, detect a first configuration channel signal of a first input signal group to determine a signal type of the first input signal group, and control the first UFP physical layer module to output the first input signal group with a first signal configuration according to the signal type of the first input signal group.

Abstract: A communication system, A power and data hub and a method for operating a communication device is disclosed, the power and data hub comprising: a hub housing; a first primary interface configured to communicate with a radio unit to communicate primary audio, primary power input, and primary data; a second primary interface configured to communicate with a communication device to communicate and/or provide secondary audio and primary power output; a first secondary interface configured to communicate and/or provide secondary data and/or secondary power output with a first peripheral device connectable to the first secondary interface; a second secondary interface configured to communicate and/or provide secondary data and/or secondary power output with a second peripheral device connectable to the second secondary interface.

Abstract: A method includes detecting, by a hardware processor and over a universal serial bus (USB) Type-A connection, whether a client controller is present in a client device. The method also includes supplying power to the client device over the USB Type-A connection by selecting between one of a first power source or a second power source depending on whether the client controller is detected.

Abstract: A power supply interface includes a first switch that couples an input terminal to an output terminal. A voltage dividing bridge is coupled to receive a supply potential. A comparator has a first input connected to a first node of the bridge and a second input configured to receive a constant potential. A digital-to-analog converter generates a control voltage that is selectively coupled by a second switch to a second node of the bridge. A circuit control controls actuation of the second switch based on operating mode and generates a digital value input to the converter based on a negotiated set point of the supply potential applied to the input terminal.

Abstract: An apparatus includes a first control unit configured to shift to at least a first power mode and a second power mode where power saving is greater than that in the first power mode, a detection unit configured to detect a predetermined return factor and output a first signal, a second control unit, which includes a storage unit storing information about input of the first signal, configured to output a second signal based on the stored information, and a third control unit configured to output a third signal for shifting the first control unit from the second power mode to the first power mode based on the second signal. The third control unit sets a predetermined value in the storage unit when the first control unit shifts to the second power mode.

Abstract: A multi-chip system and a data transmission method thereof are provided. The multi-chip system includes a first chip, a link unit, and a second chip. The first chip includes multiple transmitter (TX) channels and a first data processing module. The TX channels are configured to provide at least one transaction information. The first data processing module converts the at least one transaction information into at least one first data packet according to a general packet format and packs the at least one first data packet according to a specific packet format to generate a second data packet. The first data processing module merges two sets of second data packets into a third data packet and transmits the third data packet to the link unit. The second chip receives the third data packet through the link unit.

Abstract: An electronic device includes a first battery, a second battery, and a serial-parallel conversion circuit. The serial-parallel conversion circuit is coupled to the first battery and the second battery, and is configured to, according to a control signal, couple the first battery and the second battery in series so as to reversely charge on a to-be-charged device by the first battery and the second battery, or couple the first battery and the second battery in parallel so as to supply power to the electronic device by the first battery and the second battery.

Abstract: An apparatus includes a connector port configured to be selectably connected with and disconnected from a peripheral device. A detector is configured to provide an output indicating the connection of the peripheral device with the connector port with a time delay between connection of the peripheral device with the connector port and outputting the signal. A data switch is operatively coupled with the detector and a communication pin of the connector port and to selectably enable and disable data communication between the communication pin and a computer board in response to the output of the detector. A power switch is operatively coupled with the detector, the power supply pin, and a DC power supply and is configured to selectably connect and disconnect the power supply and the power supply pin in response to the output of the detector.

Abstract: A technique includes communicating with a plurality of input/output (I/O) modules to cause a firmware image to be transferred to the I/O modules. The I/O modules are each associated with the plurality of storage device enclosures, and the I/O modules are serially coupled together in a chain establishing a processing order among the I/O modules. The technique includes rebooting the I/O modules to cause the I/O modules to use the communicated firmware images, where the rebooting includes rebooting the I/O modules in a second order counter to the processing order.

Abstract: The examples include methods and apparatuses to power a peripheral device through a PUSB port. Powering a peripheral device through a PUSB port includes receiving a request for a plurality of PUSB power options for a PUSB port coupled to a device, providing the plurality of PUSB power options in a hardware initialization system, receiving a selection PUSB power option from the plurality of PUSB power options, and providing a power, corresponding to the selection PUSB power option, to the PUSB port.

Abstract: An aircraft-based power system includes at least one smart universal serial bus (USB-PD (Power Delivery)) outlet. The at least one smart universal serial bus (USB-PD (Power Delivery)) outlet being configured to connect to a power bus that receives power from a power source system. The at least one smart universal serial bus (USB-PD (Power Delivery)) outlet is further configured to control power delivery.

Abstract: An electronic device and a power distribution method are provided. The electronic device obtains operating power information of a first power receiving device, operating power information of a power supply device, and operating power information of at least one second power receiving device. The electronic device further dynamically adjusts power supplied from the power supply device to the first power receiving device and power supplied to the at least one second power receiving device according to the operating power information of the power supply device, the operating power information of the first power receiving device, and the operating power information of the at least one second power receiving device.

Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.

Abstract: A storage system comprises one or more storage devices, power supplies supplying power to the storage device, a processor that performs in response to determining that the total power consumption of the one or more storage devices is less than a first percentage threshold of a load of the active power supplies, deactivating one or more of the active power supplies until the total power consumption is equal to or greater than the first percentage threshold of a load of each of the active power supplies, and in response to determining that the total power consumption is equal to or greater than a second percentage threshold of a load of each of the active power supplies, activating one or more of the deactivated ones of the power supplies until the total power consumption is less than the second percentage threshold of the load of each of the active power supplies.

Abstract: A system-on-a-chip (SoC) comprises a power supply circuit coupled to an energy harvesting transducer and configured to operate using energy from the energy harvesting transducer; a microcontroller coupled to a system bus of the SoC; an interface configured to communicate with the microcontroller via the system bus of the SoC, the interface configured to generate data upon occurrence of an event; and a computation accelerator configured to establish, based on an energy consumption level of the SoC, a data path between the interface and the computation accelerator that at least partially bypasses the system bus such that the data is transmitted to the computation accelerator via the data path.

Abstract: A computing device includes a control system that communicates with multiple sensors that capture data regarding a user. The control system communicates with each of the sensors to obtain information regarding the capabilities of each sensor, and uses this capability information to determine how to configure each of the sensors. The control system also selects one of the multiple sensors to be the master sensor, and the rest of the multiple sensors are slave sensors, and notifies the multiple sensors of whether they are a slave sensor or a master sensor. The master sensor collects sensor data for the multiple sensors, capturing data itself as well as receiving data captured by the slave sensors from the slave sensors. The master sensor sends an indication of the collected data (e.g., the collected data itself or data resulting from processing the collected data) to the control system for analysis and/or processing.

Abstract: In various embodiments, rail decoupling circuits that are powered by an always on voltage rail allow a core voltage rail to power up independently of an I/O voltage rail without jeopardizing I/O pad circuits that are powered by the I/O voltage rail. In an embodiment, when the always on voltage rail is powered-up and a chip reset signal is asserted, the rail decoupling circuits drive control inputs of the I/O pad circuits based on default values. When the chip reset signal is de-asserted, the rail decoupling circuits drive the control inputs of the I/O pad circuits based on signals received from circuits powered by the core voltage rail. Because the rail decoupling circuits maintain control of the I/O pad circuits until the chip-reset is de-asserted, the core voltage rail can power up at any time before the chip-reset signal is de-asserted irrespective of when the I/O voltage rail powers up.