Abstract: A storage system comprises one or more storage devices, power supplies supplying power to the storage device, a processor that performs in response to determining that the total power consumption of the one or more storage devices is less than a first percentage threshold of a load of the active power supplies, deactivating one or more of the active power supplies until the total power consumption is equal to or greater than the first percentage threshold of a load of each of the active power supplies, and in response to determining that the total power consumption is equal to or greater than a second percentage threshold of a load of each of the active power supplies, activating one or more of the deactivated ones of the power supplies until the total power consumption is less than the second percentage threshold of the load of each of the active power supplies.

Abstract: A method for protecting operation of a server backboard is provided. The method includes: establishing an adaptive setting mechanism for an overcurrent protection point of the server backboard, where a backboard operation overcurrent protection unit is established on a server mainboard and is configured to acquire load information of a current backboard and adjust, based on the load information, an overcurrent protection point of a power supply path provided by the mainboard to the backboard; establishing an automatic current limiting mechanism applied in a case where the backboard is in an overcurrent state; and establishing a server backboard abnormality control unit.

Abstract: Embodiments generally relate to handling of NVMe scatter gather list bit bucket transfers by a data storage device. The data storage device transfers the data associated with the bit bucket transfers to a host or to a controller memory buffer of the data storage device. The data storage device can transfer the data associated with the bit bucket transfers to the host by modifying transaction layer packets (TLPs) to indicate to the host to ignore the data payload of the TLPs.

Abstract: Systems and methods are provided that may be implemented to wake an information handling system from a reduced-powered state in response to a wireless signal wake-up event received from a wireless peripheral device. Non-operating system (OS) components and/or non-BIOS components of an information handling system may be optionally enabled to securely perform pre-OS operations to determine whether or not to wake other components (e.g., such as a system OS and/or system BIOS executing on a host processing device or embedded controller) of the information handling system from a reduced-powered state upon receipt of the wireless signal wake-up event.

Abstract: A system includes a processor and a hardware accelerator coupled to the processor. The hardware accelerator includes data analysis elements configured to analyze a data stream based on configuration data and to output a result, and an integrated circuit device that includes a DMA engine that writes input data to and read output data from the data analysis elements, one or more preprocessing cores that receive the input data from the DMA engine prior to the DMA engine writing the input data to the one or more data analysis elements and perform custom preprocessing functions on the input data, and one or more post-processing cores that receive the output data from the DMA engine after the output data is read from the data analysis elements but prior to the output data being output to the processor and perform custom post-processing functions on the output data.

Abstract: An electronic device includes an interface unit having a first terminal and a second terminal, a determination unit that determines a power supply capability of an external device in accordance with a voltage of the second terminal, a power switching unit that determines a current in response to the voltage of the second terminal and a power supply capability of the external device, and a control unit that enables power supply from the external device to be performed with the determined current.

Abstract: A universal serial bus (USB) apparatus that has a USB hub, a first switching unit including first end coupled to a USB peripheral port of a first device, a second switching unit including a second end coupled to the USB hub and the first switching unit and a first end configured to be coupled to a first USB device, and control circuitry operable to provide control signals to the first and second switching units, in which the first control signals cause the first and second switching units to provide connectivity between the USB peripheral port of the first device and the first USB device when the first USB device is operating as a USB host and the second control signals to provide connectivity between the USB host port to the first USB device via the USB hub when the first USB device is operating as a USB peripheral.

Abstract: A system, apparatus and method for efficient utilization of available band-width on the system's bus connection. The system includes a scheduler configured to receive a virtual schedule that provides at least one slot for sending a message over the communication bus. A module is configured to send a message over the communication bus.

Abstract: Systems, methods, and apparatus for serial bus arbitration are described. A data communication apparatus has a bus interface circuit that uses a line driver to couple the apparatus to a data line of a serial bus. A processor in a slave device is configured to cause the apparatus to assert an in-band interrupt request on a serial bus operated in accordance with an I3C protocol, transmit a slave address of the slave device over a data line of the serial bus during a first bus arbitration transaction conducted after the in-band interrupt request is asserted, ignore signaling state of the data line while transmitting the slave address and participate in one or more transactions conducted responsive to assertion of the in-band interrupt request and transmission of the slave address. At least one other slave device transmits an address over the data line during the first bus arbitration transaction.

Abstract: In one form, an integrated circuit includes a negative voltage detector circuit and a logic circuit. The negative voltage detector circuit has a power supply input coupled to a power supply voltage terminal, a ground input coupled to a ground voltage terminal, a first input coupled to a first signal terminal, a second input coupled to a second signal terminal, and an output for providing an enable signal when a voltage on the first signal terminal is less than a voltage on the ground voltage terminal by at least a predetermined amount when a signal on said second signal terminal is in a first predetermined logic state. The logic circuit has an input for receiving the enable signal. The logic circuit changes an operation of the integrated circuit in response to an activation of the enable signal.

Abstract: A power meter includes a plurality of terminals for receiving a measure of power consumption for each of one or more phases of power that is delivered to a load as well as a controller that is operatively coupled to the plurality of terminals and is configured to determine a number of power monitor parameters based on the measure of power consumption for each of one or more phases of power. A user interface is operably coupled to the controller and is configured to display at least some of the number of power monitor parameters determined by the controller. A first communication port is operably coupled to the controller and is configured to communicate with an external device and a second communication port is operably coupled to the controller and is configured to communicate with one or more other power meters.

Abstract: A physical power supply unit (PSU) may be connected to several load subsystems. A first load subsystem may receive a first portion of a first load power directly from the physical PSU via a main power connector, the main power connector having a power limit less than the first load power. A second load subsystem may receive a second load power directly from the physical PSU to provide a second portion of the first load power to the first load subsystem via a power connection between the second load subsystem and the first load subsystem. A sum of the first portion of the first load power and the second portion of the first load power may be greater than the power limit of the main power connector.

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

Abstract: Clock-data timing in a multi-lane serial data communication link may be adjusted to compensate for drift. A reference lane may be selected and periodically trained to adjust clock-data timing. In response to initiation of a first lane transitioning from an active state to an inactive state, first information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. Then, in response to initiation of the first lane transitioning back from the inactive state to the active state, second information representing the clock-data timing of the reference lane at the time that transition is initiated may be determined. The clock-data timing of the first lane may be adjusted based on the first information and the second information.

Abstract: In at least one embodiment, a method for handling data units in a multi-user system includes granting a shared resource to a user of a plurality of users for a transaction associated with an entry of a transaction data structure. The method includes determining whether the transaction stored last partial data of a data unit associated with the user in an alignment register associated with the user. The method includes asserting a request for arbitration of a plurality of transactions associated with the plurality of users. The request is asserted for an additional transaction associated with the entry in response to determining that the transaction stored the last partial data in the alignment register. The method may include flushing the last partial data from the alignment register to a target memory in response to detecting an additional grant of the shared resource to the user for the additional transaction.

Abstract: Example apparatus, systems, and methods receive a request for data associated with an address and responsively access a memory array to obtain the data. Embodiments transition a bus from a first state to a second state and after the transitioning of the bus, drive the data onto the bus.

Abstract: A method is provided to generate a configuration descriptor for a chipset in a computing unit. The method includes determining, by one or more processors, a plurality of desired interface configurations for the chipset and for each of the one or more desired interface configurations, determining one or more ports of the chipset and corresponding platform connectors that satisfy features of the each of the one or more of the desired interface configurations based on a chipset description and a platform description. The method further includes assigning a port from among the determined one or more ports to the each of the one or more of the desired interface configurations and generating a chipset configuration descriptor based on the assigning of ports to each of the one or more desired interface configurations. In some embodiments, the chipset is initialized based on the configuration descriptor.

Abstract: Aspects of the invention include efficient generation of instrumentation data for direct memory access operations. A non-limiting example apparatus includes an instrumentation component, residing in a cache in communication with a plurality of processing units, an accelerator, and a plurality of input output interfaces. The cache includes a direct memory access monitor that receives events from the accelerator its respective I/O interface and stores DMA state and latency for each event. The cache also includes a bucket including a DMA counter and a latency counter in communication with the DMA monitor, wherein the bucket stores in the DMA counter a count of DMAs coming from a source and stores in the latency counter the latency measured for each DMA coming from the source.

Abstract: Embodiments of systems and methods for managing battery runtime based upon power source activity are described. In some embodiments, a method may include determining, based at least in part upon location and context information, that a battery of an Information Handling System (IHS) is expected to be charged by a given alternating current (AC) adapter; and modifying one or more IHS settings to reduce a power consumption of the IHS in response to the determination.

Abstract: The present disclosure generally relates to limiting bandwidth in storage devices. One or more bandwidth quality of services levels may be selected and associated with commands according to service level agreements, which may prioritize some commands over others. A storage device fetches and executes one or more the commands. Each of the commands is associated with a bandwidth quality of service level. After executing the commands and transferring the data to a host device, the storage device may delay writing a completion entry corresponding to the executed commands to a completion queue based on the associated bandwidth quality of service level of the commands. The device may then delay revealing the completion entry by delaying updating a completion queue head pointer. The device may further delay sending an interrupt signal to the host device based on the associated bandwidth quality of service level of the commands.