Abstract: A method of data transfer via a data and power connection includes determining whether a data transmission error is detected via the data and power connection. The method further includes, in response to a determination that a data transmission error is detected via the data and power connection, decreasing current across the data and power connection.

Abstract: The present invention provides an electronic device with added capabilities of preventing power supplying to an external device, and a controlling method for the electronic device. The electronic device includes: a connector capable of being connected to an external device and capable of allowing power supply to the external device; and a controlling unit configured to, in a stage before determining whether the external device has a predetermined functionality, notify the external device with information indicating first power, in a form of information indicating a power capable of being supplied to the external device. The controlling unit is also configured to, after determining that the external device has the predetermined functionality, notify the external device of information indicating second power, which is higher than the first power, in a form of information indicating a power capable of being supplied to the external device.

Abstract: Various aspects are described herein. In some aspects, the disclosure provides techniques for reducing latency in switching computing cores of a computing system between operating modes. Certain aspects provide a computing device including a plurality of computing cores, each configured to operate in any one of a plurality of operating modes. The computing device further includes a first voltage rail and a plurality of components, each associated with one of the computing cores. The computing device further includes a plurality of switches, each switch configured to selectively couple a corresponding one of the plurality of components to the first voltage rail. The computing device further includes a controller configured to determine a current operating mode of each of the plurality of computing cores and switch the plurality of switches at a first selected switching rate based on the determined current operating mode of each of the plurality of computing cores.

Abstract: Provided is a storage system that includes a plurality of storage devices; a controller that controls the storage device including a processor and a memory; and a data transfer path connecting each of the storage devices to the controller. The storage device is divided into a plurality of groups. The controller specifies the storage device belonging to each of the plurality of groups among the plurality of storage devices connected via the plurality of independent data transfer paths, receives an access request to specify the storage device to be accessed, and designates the different data transfer paths for each group of the specified storage devices. The storage device performs data transfer by a connection-less protocol according to the designated data transfer path.

Abstract: A communication device includes: a communication unit which receives control data; and a main control unit which controls an operation of the communication device, based on the control data received by the communication unit. The communication device operates in a first standby state where the main control unit stops at least a part of operations and where the communication unit detects only an access to a specific port that designates the communication device as a destination, and in a second standby state where the main control unit can execute the operations and controls the operation of the communication device, based on the control data. The communication unit wakes up the main control unit if an access to the specific port is detected in the first standby state.

Abstract: The present disclosure generally relates to a Modular PCIe Unit (MPU), which is a single-lane PCI Express endpoint that can act as either a Stand-Alone Single-Lane or as a (one) Lane in a Multilane Endpoint Unit, composed by cascaded-MPUs. The MPU will include a PCIe link, a PCIe transition, a SoC specific and a PCIe phy that are all unique to the individual MPU. The MPUs are scalable in that a single MPU may be used or, if more MPUs are desired for higher performance, additional MPUs, each of which can be unique, added to create the Multilane Endpoint Unit.

Abstract: Logic of a handheld controller can implement sensor fusion algorithms based on force data provided by a force sensing resistor (FSR) in combination with touch data or proximity data provided by a touch sensor or an array of proximity sensors, respectively. An example sensor fusion algorithm can be used to re-calibrate the FSR when an object contacts an associated control, as detected by the touch sensor. Another example sensor fusion algorithm can be used to ignore spurious inputs detected by the FSR when an object is in contact with an adjacent control. Another example sensor fusion algorithm can be used to detect a hand size of a hand grasping a handle of the controller, as detected by the array of proximity sensors, and to adjust the threshold force to register a FSR input event at the FSR according to the hand size.

Abstract: A data processing system is disclosed that includes an Input/output (I/O) interface to receive incoming data and an in-line accelerator coupled to the I/O interface. The in-line accelerator is configured to receive the incoming data from the I/O interface and to automatically remove all timing channels that potentially form through any shared resources. A generic technique of the present design avoids timing channels between different types of resources. A compiler is enabled to automatically apply this generic pattern to secure shared resources.

Abstract: Systems, methods, and apparatus are described that enable a serial bus to be operated in one or more modes that employ additional wires for communicating data. A method includes providing a data payload for a first data frame to be transmitted over a plurality of data lanes of a multilane serial bus operated in accordance with an I3C protocol, providing one or more indicators of validity of one or more bytes included in the data payload, and transmitting the first data frame over the multilane serial bus in accordance with a clock signal transmitted on a clock lane of the multilane serial bus.

Abstract: A liquid crystal display device is disclosed. The liquid crystal display device includes: a display unit; and first to n-th control units configured to control respective areas of the display unit, where n is an integer greater than or equal to 2, wherein: each of the first to (n?1)-th control units is provided with a unidirectional channel linking that control unit to a following one of the control units that is assigned a next greater ordinal number; the n-th control unit is provided with a unidirectional channel linking the control unit to the following, first control unit; and each of the control units, based on a state of that control unit and also on a link signal received from a preceding one of the control units, transmits a link signal to a following one of the control units and controls an associated one of the areas.

Abstract: Described is a reconfigurable transmitter which includes: a first pad; a second pad; a first single-ended driver coupled to the first pad; a second single-ended driver to the second pad; a differential driver coupled to the first and second pads; and a logic unit to enable of the first and second single-ended drivers, or to enable the differential driver.

Abstract: A machine implemented method for prioritizing system interrupts in a processing system is provided. The method comprising: determining, at a supervisor module, for each interrupt, a relative interrupt priority in accordance with at least one interrupt parameter for said interrupt; prioritising, at said supervisor module, each said interrupt with respect to other interrupts of said system in compliance with said determined relative interrupt priority; and in response to a change to said at least one interrupt parameter during operation of said system, adjusting said determined relative interrupt priority, and re-prioritising each said interrupt with respect to said other interrupts of said system in compliance with said adjusted relative interrupt priority.

Abstract: Logic of a handheld controller can implement sensor fusion algorithms based on force data provided by a force sensing resistor (FSR) in combination with touch sensor data provided by a touch sensor. An example sensor fusion algorithm can be used to pause calibration adjustments for the touch sensor—at least with respect to a high-level value that corresponds to a touch of a control—in response to a user pressing upon the control of the handheld controller with an above-threshold amount of force, which may be detected by a FSR associated with the control. For instance, calibration adjustments with respect to the high-level value can be paused in response to FSR values crossing a threshold value from below the threshold value to above the threshold value, and the calibration adjustments can be resumed in response to the FSR values crossing the threshold value in the opposite direction.

Abstract: An illumination dummy module is adapted for covering and protecting a card slot and includes a circuit board, a power pin, a clock pin, a data pin, at least one light source, a power converter, and a drive circuit. The circuit board includes an insertion part for inserting into the card slot. The power pin, the clock pin and the data pin are disposed to the insertion part, and the light source is disposed on the circuit board. The power converter receives input power from the card slot via the power pin, and converts the input power into output power. The drive circuit is disposed on the circuit board, and receives the output power from the power converter. The drive circuit also respectively receives a clock signal and a control command via the clock pin and the data pin, to enable or disable the light source.

Abstract: A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.

Abstract: The present disclosure generally relates to limiting bandwidth in storage devices. One or more bandwidth quality of services levels may be selected and associated with commands according to service level agreements, which may prioritize some commands over others. A storage device fetches and executes one or more the commands. Each of the commands is associated with a bandwidth quality of service level. After executing the commands and transferring the data to a host device, the storage device may delay writing a completion entry corresponding to the executed commands to a completion queue based on the associated bandwidth quality of service level of the commands. The device may then delay revealing the completion entry by delaying updating a completion queue head pointer. The device may further delay sending an interrupt signal to the host device based on the associated bandwidth quality of service level of the commands.

Abstract: A data method and a related device to resolve a disadvantage encountered when a first device accesses data of a second device. The method is applied to the first device, and the first device is coupled to the second device using a Universal Serial Bus (USB) interface. The method includes displaying, by the first device, an interface to which the second device is mapped, accessing data of the second device using the interface, receiving, by the first device, an instruction entered for the interface, displaying the data of the second device, receiving, by the first device, an operation instruction entered for the data, and processing, by the first device, the data according to the operation instruction.

Abstract: In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.

Abstract: Systems and/or methods are provided that facilitate employing a variable read latency on a serial memory bus. In an aspect, a memory can utilize an undefined amount of time to obtain data from a memory array and prepare the data for transfer on the serial memory bus. The serial memory bus can be driven to a defined state. When data is ready for transfer, the memory can assert a start bit on the serial memory bus to notify a host prior to initiating the data transfer.

Abstract: A system includes a processor and a hardware accelerator coupled to the processor. The hardware accelerator includes data analysis elements configured to analyze a data stream based on configuration data and to output a result, and an integrated circuit device that includes a DMA engine that writes input data to and read output data from the data analysis elements, one or more preprocessing cores that receive the input data from the DMA engine prior to the DMA engine writing the input data to the one or more data analysis elements and perform custom preprocessing functions on the input data, and one or more post-processing cores that receive the output data from the DMA engine after the output data is read from the data analysis elements but prior to the output data being output to the processor and perform custom post-processing functions on the output data.