Abstract: A semiconductor device includes a semiconductor substrate and a p-doped layer formed on the substrate having a dislocation density exceeding 108 cm?2. An n-type layer is formed on or in the p-doped layer. The n-type layer includes a II-VI material configured to tolerate the dislocation density to form an electronic device with reduced leakage current over a device with a III-V n-type layer.

Abstract: An organic light emitting device including: a base substrate; column banks extending in one direction along a surface of the base substrate; and light emitting elements extending along the one direction in groove regions defined by the column banks, wherein each of the light emitting elements has one or more functional layers sandwiched between a pair of electrodes, and within at least one of the groove regions: a sub-bank extends along the one direction and has a height equal to or smaller than a height of the column banks, and for each of the one or more functional layers therein, portions thereof on either side of the sub-bank are made of the same material.

Abstract: An electrode structure of an LED includes an adhesion layer and a bond pad layer. The adhesion layer is stacked on the LED. The bond pad layer is stacked on the adhesion layer. The bond pad layer includes at least two first metal layers, at least two second metal layers and an outermost gold layer sequentially and alternately stacked. The first metal layers are selected from the group consisting Al and an Al alloy, and the second metal layers are selected from the group consisting of Ti, Ni, Cr, Pt, Pd, TiN, TiW, W, Rh and Cu. Thus, the main structure of the bond pad layer is a stacked structure of the first metal layers and the second metal layers. The first metal layers may be selected from a low-cost material, and the second metal layers improve issues of inadequate hardness and electromigration of the first metal layers.

Abstract: The invention provides a TFT backplane structure and manufacturing method thereof. The TFT backplane structure uses the three-layered structure, from bottom up, dielectric layer (41), SiNx layer (42), and SiO2 layer (43), for the gate insulating layer (4) corresponding to the location of the TFT (T), to enhance the TFT reliability; uses a double-layered gate insulating layer (4), from bottom up, the dielectric layer (41), and at least a portion of SiNx layer (42), at the location corresponding to the storage capacitor (C), or a single-layered gate insulating layer (4), i.e., the dielectric layer (4), at the location corresponding to the storage capacitor (C), the dielectric constant can be increased, the distance between the two storage capacitor electrode plates is reduced, resulting in reducing the capacitor area and improve aperture ratio on the premise of storage capacitance performance.

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.

Abstract: An electronic device can include a first transistor including a first gate electrode; and a second transistor including a second gate electrode. The first and second transistors can be electrically connected in a parallel arrangement, wherein the transistors have one or more different characteristics. For example, gate length, barrier layer thickness, gate-to-drain distance, leakage current, on-state electron density, or the like may be different between the transistors. The difference in characteristics can help to reduce degradation and improve the lifetime of the first transistor.

Abstract: The present invention relates to a method for machining a blank (10) by means of a tool (12) for producing a finished part, wherein the tool (12) is moved during the machining on a guide path (14) comprising at least three successive path segments (16, 18, 20; 16-1, 18-1, 20-1; 16-2, 18-2, 20-2; 18?) in the form of two machining segments (16, 20; 16-1, 20-1; 16-2, 20-2) and one connecting segment (18; 18-1; 18-2; 18?), which connects the two machining segments (16, 20; 16-1, 20-1; 16-2, 20-2) to one another, and wherein the connecting segment (18; 18-1; 18-2; 18?) of the path segments (16, 18, 20; 16-1, 18-1, 20-1; 16-2, 18-2, 20-2; 18?), which connecting segment connects the two machining segments (16, 20; 16-1, 20-1; 16-2, 20-2), is determined in terms of its shape by the forward feed (F1) of the tool (12) at the end (24) of the first machining segment (16) and by the forward feed (F2) of the tool (12) at the start (30) of the second machining segment (20).

Abstract: A three dimensional semiconductor device, comprising: a substrate including a plurality of circuits; a plurality of pads, each pad coupled to a circuit; and a memory array positioned above or below the substrate and coupled to a circuit to program the memory array.

Abstract: A passive device and method of fabricating the passive device are disclosed herein. The capacitor structure incorporates a resistor and a capacitor. An exemplary method includes receiving a substrate that has undergone front end of line (FEOL) processing, and performing back end of line (BEOL) processing on the substrate, wherein a capacitor structure is formed over the substrate during the BEOL processing, the capacitor structure incorporating a resistor with a capacitor. The BEOL processing can include performing a first metallization process to form a bottom plate of the capacitor structure; forming a dielectric spacer of the capacitor structure over the bottom plate; forming a top plate of the capacitor structure over the dielectric spacer; and performing a second metallization process to form contacts coupled to the top plate and the bottom plate of the capacitor structure.

Abstract: Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (Fe). In some embodiments, the magnetic interface region is spaced from at least one oxide-based region by a magnetic region. The presence of the magnetic interface region enhances the perpendicular magnetic anisotropy (PMA) strength of the magnetic cell core. In some embodiments, the PMA strength may be enhanced more than 50% compared to that of the same magnetic cell core structure lacking the magnetic interface region.

Abstract: A high electron mobility transistor includes a first III-V compound layer, a second III-V compound layer, a source electrode, a drain electrode, a gate electrode, a first moat, and a second moat. The second III-V compound layer is disposed on the first III-V compound layer. The source electrode and the drain electrodes are disposed above the first III-V compound layer. The gate electrode is disposed above the second III-V compound layer located between the source and the drain electrodes in a first direction. The second III-V compound layer includes a first region under the gate electrode. The first moat is at least partially disposed between the first region and the source electrode in the first direction. The second moat is at least partially disposed between the first region and the drain electrode in the first direction.

Abstract: The invention provides a recess structure for print deposition process and manufacturing method thereof. By disposing the dam (2) enclosing the recess (3) as comprising at least two stacked branch dam layers, and increasing the contact angle between the inclined inner circumferential surface of recess (3) enclosed by the branch dam layers and ink in a layer-by-layer manner, to limit height the ink able to climb on the inclined inner circumferential surface of the recess (3), the invention can improve the thickness uniformity of the organic functional layers printed in the recess and the photoelectric properties of organic functional layers. The recess (3) fabricated by the manufacturing method can limit height the ink able to climb on inclined inner circumferential surface of the recess (3) to improve the thickness uniformity of the organic functional layers printed in the recess and the photoelectric properties of organic functional layers.

Abstract: A semiconductor structure is provided that contains a plurality of vertically stacked and spaced apart semiconductor nanosheets in which an inner dielectric liner and an air gap are present. Collectively, each inner spacer and air gap combination provides an inner spacer structure that separates a portion of a functional gate structure that surrounds each semiconductor nanosheet from a portion of a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure.

Abstract: An integrated circuit device can include a substrate having a first area and a second area and a pair of first fin-shaped active areas each having a first shape protruding from the first area in a first direction, adjacent to each other, and extending in a straight line. A fin separation insulating film can be between the pair of first fin-shaped active areas in the first area and a second fin-shaped active area can protrude from the second area in the first direction and have a second shape that is different from the first shape, wherein respective widths of each of the pair of first fin-shaped active areas are less than a corresponding width of the second fin-shaped active area.

Abstract: A method for making a oxide semiconductor film includes a step of forming an oxide film on a substrate by using a sputtering method and a sputtering target comprising In2CexZnO4+2x, wherein x=0.5˜2.

Abstract: A light emitting structure includes a first hole injection layer, a first organic light emitting layer, a charge generation layer, a second hole injection layer, a second organic light emitting layer, an electron transfer layer, and a blocking member. The light emitting structure has first, second, and third sub-pixel regions. The first organic light emitting layer may be on the first hole injection layer. The charge generation layer may be on the first organic light emitting layer. The second hole injection layer may be on the charge generation layer. The second organic light emitting layer may be on the second hole injection layer. The electron transfer layer may be on the second organic light emitting layer. The blocking member may be at at least one of the first to the third sub-pixel regions.

Abstract: A method for fabricating semiconductor device is disclosed. First, a substrate is provided, a first gate structure is formed on the substrate, a first spacer is formed around the first gate structure, and an interlayer dielectric (ILD) layer is formed around the first spacer. Next, a first etching process is performed to remove part of the ILD layer for forming a recess, a second etching process is performed to remove part of the first spacer for expanding the recess, and a contact plug is formed in the recess.

Abstract: Disclosed is an integrated circuit comprising a substrate carrying a plurality of circuit elements; a metallization stack interconnecting said circuit elements, said metallization stack comprising a patterned upper metallization layer comprising a first metal portion; a passivation stack covering the metallization stack; and a sensor including a sensing material on the passivation stack, said sensor being coupled to the first metal portion by a via extending through the passivation stack. A method of manufacturing such an IC is also disclosed.

Abstract: Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.

Abstract: In an aspect, a flexible substrate may include a base substrate, an insulating layer positioned on a first surface of the base substrate, a protective film positioned on a second surface facing the first surface of the base substrate and an adhesive layer positioned between the base substrate and the protective film and attaching the protective film on the second surface of the base substrate. The adhesive layer may include a cross-linker.