Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.

Abstract: A method for forming a transistor is provided. The method includes providing a semiconductor substrate, and forming a dielectric layer on the semiconductor substrate. The dielectric layer has a gate structure recess. The method also includes forming a work function layer on a bottom and sidewalls of the gate structure recess; performing an ion implantation on the work function layer; and forming a gate layer on the work function layer after the ion implantation.

Abstract: Systems and methods for automated maintenance of the top and bottom surfaces or skins of an integrally stiffened hollow structure (e.g., a horizontal stabilizer) using surface crawling vehicles. Each system uses dynamically controlled magnetic coupling to couple an external drive tractor to a pair of passive trailers disposed in the interior of the hollow structure on opposite sides of a vertical structural element. The external drive tractor is also coupled to an external maintenance tool, which the tractor pushes or pulls across the surface skin to perform a maintenance function. The systems allow maintenance operations to be performed on both surface skins without turning the hollow structure over. Each system is modular and can be transported to and easily set up in a building or factory.

Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.

Abstract: A semiconductor device including a transistor is provided. The transistor includes a gate electrode, a first insulating film over the gate electrode, a second insulating film over the first insulating film, an oxide semiconductor film over the second insulating film, a source electrode and a drain electrode electrically connected to the oxide semiconductor film, a third insulating film over the source electrode, and a fourth insulating film over the drain electrode. A fifth insulating film including oxygen is provided over the transistor. The third insulating film includes a first portion, the fourth insulating film includes a second portion, and the fifth insulating film includes a third portion. The amount of oxygen molecules released from each of the first portion and the second portion is smaller than the amount of oxygen molecules released from the third portion when the amounts are measured by thermal desorption spectroscopy.

Abstract: Transistor devices and fabrication methods are provided. A transistor is formed by forming a dummy gate film on a substrate and doping an upper portion of the dummy gate film to form a modified film. The modified film and the remaining dummy gate film are etched to form a modified layer and a dummy gate layer on the substrate. Source/drain regions are formed in the substrate and on both sides of the dummy gate layer. A dielectric film is formed on each of the substrate, the source/drain regions, and the dummy gate layer. The dielectric film and the modified layer are planarized to provide a dielectric layer, and to remove the modified layer and expose the dummy gate layer. The dielectric film has a planarization rate lower than the modified layer, and the formed dielectric layer has a surface higher than the exposed dummy gate layer.

Abstract: A method for integrating nanostructures in finFET processing and a related device are provided. Embodiments include forming fins in a Si substrate in first and second device regions; forming STI regions in spaces between fins; forming a first hardmask over the fins and STI regions; removing a portion of the first hardmask over the first device region to expose upper surfaces of the fins and STI regions in the first device region; recessing an upper portion of the fins; forming first devices over the recessed fins; forming a second hardmask over the fins and STI regions; removing a portion of the second hardmask over the second device region to expose upper surfaces of the fins and STI regions; recessing an upper portion of the fins; and forming second devices, different from the first devices, over the recessed fins, wherein the first and/or second devices include nanowire or nanosheet devices.

Abstract: A silicon carbide semiconductor substrate includes: a base substrate that has a main surface having an outer diameter of not less than 100 mm and that is made of single-crystal silicon carbide; and an epitaxial layer formed on the main surface. The silicon carbide semiconductor substrate has an amount of warpage of not less than ?100 ?m and not more than 100 ?m when a substrate temperature is a room temperature and has an amount of warpage of not less than ?1.5 mm and not more than 1.5 mm when the substrate temperature is 400° C.

Abstract: A waterless vacuum based smoking apparatus utilizes vacuum created by translation of a cartridge within a chamber of a sheath body in order to accumulate within the chamber smoke or vapor from a combustible or vaporizable substance, which can then be expelled for inhalation by a user by reversing the translation of the cartridge within the chamber. Measurement and tracking functionalities are provided so that a user may accurately assess and monitor their intake.

Abstract: A layer stack including an alternating stack of insulating layers and sacrificial material layers is formed over a substrate. After formation of memory stack structures, backside trenches are formed through the layer stack. The sacrificial material layers are replaced with electrically conductive layers. Drain select level dielectric isolation structures are formed through drain select level of the stack after formation of the electrically conductive layers. The drain select level dielectric isolation structures laterally separate portions of conductive layers that are employed as drain select level gate electrodes for the memory stack structures.

Abstract: A semiconductor device and a fabrication method are provided. The semiconductor device is fabricated by providing a substrate with a device area surrounded by a seal ring area, forming a buried deep-well layer in the substrate of the seal ring area, forming a first well region and a second well region in the substrate above the buried deep-well layer with the first well region surrounding the device area and the second well region surrounding the first well region, forming a heavily doped region in the substrate above the buried deep-well layer and between the first well region and the second well region, and forming a seal ring structure connecting to the heavily doped region. The buried deep-well layer, the first well region, and the second well region all have a first doping type while the heavily doped region and the substrate have a second doping type.

Abstract: A capacitive device includes a first electrode comprising a nanosheet stack and a second electrode comprising a nanosheet stack, the second electrode arranged substantially parallel to the first electrode. A first conductive contact is arranged on a basal end of the first electrode, and a second conductive contact is arranged on a basal end of the second electrode.

Abstract: The present application discloses a thin film transistor including a base substrate; an active layer on the base substrate having a first semiconductor region, a second semiconductor region, and a plurality of semiconductor bridges each of which connecting the first semiconductor region and the second semiconductor region; the plurality of semiconductor bridges spaced apart from each other; the active layer being made of a material including M1OaNb, wherein M1 is a single metal or a combination of metals, a>0, and b?0; an etch stop layer on a side of the active layer distal to the base substrate; the first semiconductor region having a first non-overlapping portion, a projection of which is outside that of the etch stop layer in plan view of the base substrate; the second semiconductor region having a second non-overlapping portion, a projection of which is outside that of the etch stop layer in plan view of the base substrate; a first electrode on a side of the first non-overlapping portion distal to the

Abstract: A device is disclosed. The device comprises a substrate having an epitaxial layer of a first conductivity type, a deep trench of a first depth, a pillar region of a second conductivity type of a second depth and a blocking layer of a third conductivity type immediately below a bottom surface of the deep trench. The second depth is larger than the first depth.

Abstract: A semiconductor device includes a semiconductor substrate, at least a first fin structure, at least a second fin structure, a first gate, a second gate, a first source/drain region and a second source/drain region. The semiconductor substrate has at least a first active region to dispose the first fin structure and at least a second active region to dispose the second fin structure. The first/second fin structure partially overlapped by the first/second gate has a first/second stress, and the first stress and the second stress are different from each other. The first/second source/drain region is disposed in the first/second fin structure at two sides of the first/second gate.

Abstract: An optical fingerprint identification module includes a casing, an image pickup assembly, a light-guiding diffusion layer, a light-collecting reflective layer, a press plate, a light source and an optical tunnel structure. The optical tunnel structure is located under the press plate and located over the image pickup assembly. The optical tunnel structure is penetrated through the light-collecting reflective layer and a part of the light-guiding diffusion layer. After a light beam emitted by the light source is introduced into the light-guiding diffusion layer, the light beam is guided and diffused by the light-guiding diffusion layer and collected and reflected by the light-collecting reflective layer. Consequently, the light beam is transferred between the light-guiding diffusion layer and the light-collecting reflective layer. After the light beam is irradiated on the press plate through the optical tunnel structure, the light beam is reflected to the image pickup assembly.

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

Abstract: Embodiments relate to buried structures for silicon devices which can alter light paths and thereby form light traps. Embodiments of the lights traps can couple more light to a photosensitive surface of the device, rather than reflecting the light or absorbing it more deeply within the device, which can increase efficiency, improve device timing and provide other advantages appreciated by those skilled in the art.

Abstract: In various embodiments, a method for forming a memory array includes forming a plurality of rows and columns of hardmask material, etching holes in the one or more layers of insulating material using the combined masking properties of the rows of hardmask material and the columns of hardmask material, and forming memory cells in the holes. The corners of the holes can be rounded.

Abstract: A conductive layer is formed on the first zone of a carrier. The redistribution layer is formed on the conductive layer on the first zone and the second zone of the carrier. Then an open-test and a short-test are performed to the redistribution layer. Since the conductive layer and the parts of the redistribution layer formed on the conductive layer constitute a closed loop, a load is presented if the redistribution layer is formed correctly. In addition, no load is presented if the redistribution layer is formed correctly since the parts of the redistribution layer formed on the second zone of the carrier constitute an open loop. Therefore, whether the redistribution layer is flawed or not is determined before the dies are boned on the redistribution layer. Thus, no waste of the good die is occurred because of the flawed redistribution layer.