Abstract: Provided is a novel semiconductor device. The semiconductor device comprises a first transistor and a second transistor. The first transistor comprises a first gate electrode; a first insulating film over the first gate electrode; a first oxide semiconductor film over the first insulating film; a first source electrode and a first drain electrode over the first oxide semiconductor film; a second insulating film over the first oxide semiconductor film, the first source electrode, and the first drain electrode; and a second gate electrode over the second insulating film.

Abstract: Magnetic memory cells, methods of fabrication, semiconductor device structures, and memory systems are disclosed. A magnetic cell core includes at least one magnetic region (e.g., a free region or a fixed region) configured to exhibit a vertical magnetic orientation, at least one oxide-based region, which may be a tunnel junction region or an oxide capping region, and at least one magnetic interface region, which may comprise or consist of iron (Fe). In some embodiments, the magnetic interface region is spaced from at least one oxide-based region by a magnetic region. The presence of the magnetic interface region enhances the perpendicular magnetic anisotropy (PMA) strength of the magnetic cell core. In some embodiments, the PMA strength may be enhanced more than 50% compared to that of the same magnetic cell core structure lacking the magnetic interface region.

Abstract: Collision-free movement of a mobile medical device, such as a mobile medical imaging device, in a room is controlled via a man-machine interface. A model of the room environment is created and displayed, together an actual position of the medical device. The room model and the actual position are based at least in part on real-time sensor data. A destination position for the medical device is entered, the entered destination position is displayed and a collision-free movement path is generated from the actual position to the destination position. The movement path is displayed in the room model. A movement command relating to the displayed movement path is entered and the medical device is driven along the entered movement path from the actual position to the destination position.

Abstract: A method includes oxidizing a semiconductor fin to form an oxide layer on opposite sidewalls of the semiconductor fin. The semiconductor fin is over a top surface of an isolation region. After the oxidizing, a tilt implantation is performed to implant an impurity into the semiconductor fin. The oxide layer is removed after the tilt implantation.

Abstract: A TFT backplane structure includes a gate insulating layer that includes a three-layered portion, which includes, from bottom up, a dielectric layer, a SiNx layer, and a SiO2 layer, set at a location corresponding to a TFT in order to enhance the TFT reliability, and also includes a double-layered portion, which includes from bottom up, the dielectric layer and at least a portion of the SiNx layer, set at a location corresponding to a storage capacitor, or alternatively a single-layered structure that includes only the dielectric layer set at the location corresponding to the storage capacitor so that the dielectric constant can be increased, the distance between the two storage capacitor electrode plates is reduced, resulting in reducing the capacitor area and improve aperture ratio on the premise of storage capacitance performance.

Abstract: A pixel structure, a display panel and a manufacturing method of the pixel structure are disclosed. The pixel structure includes: gate lines extending in parallel in a first direction; data lines extending in parallel in a second direction; and a plurality of pixel units defined by the gate lines and the data lines. One of the data lines is disposed between two pixel units which are adjacent to each other in the first direction, and two of the gate lines are disposed between two pixel units which are adjacent to each other in the second direction. Each of the pixel units comprises two pixel regions which are arranged side by side in the first direction, each of the pixel regions comprises a pixel electrode, and each of the pixel units comprises a unitary common electrode which covers the two pixel regions.

Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.

Abstract: The present application provides an LTPS multilayered structure, which includes: a first stack layer having a reference pattern structure formed thereon and provided with uniformly distributed first references; and a second stack layer disposed on the first stack layer and having an alignment pattern structure formed thereon and provided with uniformly distributed second references each selectively aligning with one of the first references so that misalignment between the first stack layer and the second stack layer is precisely calculated by markings attached to each of the first references. The present further provides a method for measuring misalignment between a plurality of stack layers in the LTPS multilayered structure.

Abstract: A numerical control apparatus has a detector, a condition generator, and a logging processor. The detector detects occurrence of a preset event. The condition generator acquires, as a reference value, first numerical control information at a timing when the occurrence of the event is detected, and performs preset first arithmetic processing by using the reference value to generate a first determination condition. When the first numerical control information satisfies the first determination condition, the logging processor starts a process of logging second numerical control information.

Abstract: The disclosure relates to method and apparatus for micro-contact printing of micro-electromechanical systems (“MEMS”) in a solvent-free environment. The disclosed embodiments enable forming a composite membrane over a parylene layer and transferring the composite structure to a receiving structure to form one or more microcavities covered by the composite membrane. The parylene film may have a thickness in the range of about 100 nm-2 microns; 100 nm-1 micron, 200-300 nm, 300-500 nm, 500 nm to 1 micron and 1-30 microns. Next, one or more secondary layers are formed over the parylene to create a composite membrane. The composite membrane may have a thickness of about 100 nm to 700 nm to several microns. The composite membrane's deflection in response to external forces can be measured to provide a contact-less detector. Conversely, the composite membrane may be actuated using an external bias to cause deflection commensurate with the applied bias.

Abstract: After forming a gate structure over a semiconductor fin that extends upwards from a semiconductor substrate portion, a sigma cavity is formed within the semiconductor fin on each side of the gate structure. A semiconductor buffer region composed of an un-doped stress-generating semiconductor material is epitaxially growing from faceted surfaces of the sigma cavity. Finally, a doped semiconductor region composed of a doped stress-generating semiconductor material is formed on the semiconductor buffer region to completely fill the sigma cavity. The doped semiconductor region is formed to have substantially vertical sidewalls for formation of a uniform source/drain junction profile.

Abstract: In one embodiment, a pixel for an electronic display includes a first subpixel, a second subpixel stacked on top of the first subpixel, and a third subpixel stacked on top of the second subpixel. Each of the first, second, and third subpixels comprises a polygon shape. Each of the first, second, and third subpixels comprises an emissive layer, a transparent cathode layer, and a transparent anode layer.

Abstract: A semiconductor structure is provided that contains a plurality of vertically stacked and spaced apart semiconductor nanosheets in which an inner spacer liner and an air gap are present. Collectively, each inner spacer liner and air gap combination provides an inner spacer structure that separates a portion of a functional gate structure that surrounds each semiconductor nanosheet from a portion of a source/drain (S/D) semiconductor material structure that is present on each side of the functional gate structure.

Abstract: A method of forming multiple vertical transport fin field effect transistors (VT FinFETs) having different channel lengths, including, forming a vertical fin on a first region of a substrate and a vertical fin on a second region of the substrate, forming a cover block on the vertical fin on the second region of the substrate, forming a first bottom source/drain on the first region of the substrate, wherein the first bottom source/drain covers a lower portion of the vertical fin on the first region, removing the cover block, and forming a second bottom source/drain in the second region of the substrate, wherein the second bottom source/drain is below the surface of the substrate, wherein the second bottom source/drain does not cover a lower portion of the vertical fin on the second region.

Abstract: A display device comprises a substrate having a foldable first region and a second region adjacent to the foldable first region, wherein a folding axis overlaps the foldable first region. The display device further comprises a first transistor overlapping the foldable first region and having a first channel region with a first dimension along a first direction that is substantially perpendicular to the folding axis. The display device further comprises a second transistor overlapping the second region and having a second channel region with a second dimension along the first direction, wherein the first dimension is less than the second dimension.

Abstract: A semiconductor device including a semiconductor substrate; a conductive film covering a front face of the semiconductor substrate, a front face of the conductive film having plural straight-line shaped concave portions disposed in parallel to each other; and a protecting film covering the front face of the conductive film, the protecting film having an opening that has an edge forming an angle with the plural concave portions of greater than 0° and less than 90°, and that partially exposes the conductive film.

Abstract: A multi-channel thin film transistor (“TFT”) includes: a gate electrode; a semiconductor including a first channel area, which operates within a first driving range and has a first threshold voltage, and a second channel area which operates within a second driving range smaller than the first driving range and has a second threshold voltage, where an absolute value of the second threshold voltage is greater than an absolute value of the first threshold voltage; a first electrode connected to an end of the semiconductor; and a second electrode connected to another end of the semiconductor.

Abstract: An insulator is formed by flowable chemical vapor deposition (FCVD) process. The insulator is cured by exposing the insulator to ultraviolet light while flowing ozone over the insulator to produce a cured insulator. The curing process forms nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters in the insulator. Following the curing process, these methods select wavelengths of microwave radiation (that will be subsequently used during annealing) so that such wavelengths excite the nitrogen, hydrogen, nitrogen monohydride, or hydroxyl-rich atomic clusters. Then, these methods anneal the cured insulator by exposing the cured insulator to microwave radiation in an inert (e.g., non-oxidizing) ambient atmosphere, at a temperature below 500° C., so as to increase the density of the cured insulator.

Abstract: Multilayer dielectric structures are provided with graded composition. For example, a multilayer dielectric structure includes a stack of dielectric films, wherein the dielectric films include at least a first SiCNO (silicon carbon nitride oxide) film and a second SiCNO film. The first SiCNO film has a first composition profile of C, N, and O atoms. The second SiCNO film has a second composition profile of C, N, and O atoms, which is different from the first composition profile of C, N, and O atoms. The composition profiles of C, N and/or O atoms of the constituent dielectric films of the multilayer dielectric structure are customized to enhance or otherwise optimize one or more electrical and/or physical properties of the multilayer dielectric structure.

Abstract: A manufacturing method of a metal layer, a functional substrate and a manufacturing method thereof, and a display device are provided. The manufacturing method of a metal layer includes: forming an insulating layer on a base substrate; forming an etching buffer layer on the insulating layer; patterning the etching buffer layer and the insulating layer to form a plurality of recessed microstructures in the insulating layer; stripping the etching buffer layer; and forming a metal layer on the insulating layer, a surface of the metal layer adjacent to the insulating layer is formed with a plurality of protruded portions which are filled into the plurality of recessed microstructures. The manufacturing method of a metal layer may form a metal layer with anti-reflection effect.