Patents Examined by Thomas L Dickey
  • Information processing equipment and method for controlling information processing equipment
    Patent number: 10203670
    Abstract: Information processing equipment includes: arithmetic processing units configured to execute jobs, respectively; a supply channel through which a coolant flows, the coolant absorbing heat generated by the arithmetic processing units; a circulating device configured to circulate the coolant in the supply channel through an outlet to output the coolant; and a job allocation device configured to allocate a job, when allocating the jobs to the arithmetic processing units, to a job non-execution arithmetic processing unit, if any, that is the arithmetic processing unit executing no job among the arithmetic processing units, the job non-execution arithmetic processing unit being positioned closer to the outlet side on the supply channel.
    Type: Grant
    Filed: May 19, 2015
    Date of Patent: February 12, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Jumpei Kubota
  • Light-emitting device
    Patent number: 10199542
    Abstract: A light-emitting device comprises a semiconductor stack; a pad electrode comprising a periphery disposed on the semiconductor stack; and a finger electrode connected to the pad electrode, wherein the finger electrode comprises a first portion extended from the periphery of the pad electrode and a second portion away from the pad electrode, the first portion comprises a first side and a second side, the first side is opposite to the second side, the first side comprises a first arc having a first curvature radius, and the first curvature radius is larger than 10 ?m.
    Type: Grant
    Filed: October 24, 2016
    Date of Patent: February 5, 2019
    Assignee: EPISTAR CORPORATION
    Inventors: Chien-Hua Chou, Tai-Chun Wang, Chih-Tsung Su, Biau-Dar Chen
  • Display unit and electronic apparatus
    Patent number: 10199606
    Abstract: A display unit of the present disclosure includes: a plurality of pixels that are disposed in a regular manner; a plurality of first openings that are provided in each of the plurality of pixels; and one or more second openings that are provided in at least a portion of a peripheral edge of each of the plurality of pixels that are disposed in a regular manner.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: February 5, 2019
    Assignee: Sony Corporation
    Inventors: Kazuma Teramoto, Takahide Ishii, Kaoru Abe
  • Control device of electrical apparatus and energy management system
    Patent number: 10191459
    Abstract: A control device of an electrical apparatus configured to receive power from a facility that receives a supply of power from a system power supply, the facility including an energy management system that manages a power feeding schedule according to a first management function provided for managing the power feeding schedule for feeding power to the electrical apparatus, the control device includes an electronic control unit configured to: communicate with the energy management system; manage the power feeding schedule according to a second management function provided for managing the power feeding schedule in the control device; and determine whether the electronic control unit or the energy management system of the facility, will manage the power feeding schedule by comparing the first management function of the energy management system and the second management function of the control device.
    Type: Grant
    Filed: March 8, 2016
    Date of Patent: January 29, 2019
    Assignee: TOYOTA JIDOSHA KABUSHIKI KAISHA
    Inventor: Tomoya Oono
  • Electrostatic discharge protection structure and fabricating method thereof
    Patent number: 10186507
    Abstract: An electrostatic discharge protection structure and a fabricating method thereof are provided. The electrostatic discharge protection structure comprises: a substrate; multiple fin portions arranged on the substrate; a gate structure on the substrate across the fin portions, and on a portion of top surfaces and sidewalls of the fin portions; a first groove in the substrate and overlapping with a first extension pattern of the fin portions; a first doped epitaxial layer filled within the first groove, and being used as a source; a second groove in the substrate and overlapping with a second extension pattern of the fin portions; and a second doped epitaxial layer filled within the second groove, and being used as a drain.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: January 22, 2019
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION
    Inventor: Yong Li
  • MOS-bipolar device
    Patent number: 10170605
    Abstract: A clustered Insulated Gate Bipolar Transistor (CIGBT) comprising a drift region (24), a P region (20) formed within the n-type drift region, an N well region (22) formed within the P well region (20), a P base region (32) formed within the N well region (22) and a cathode region (36). One or more trenches (40) are formed in the device and configured to longitudinally intersect the drift region (24) and, optionally, the P well region (20) as well as laterally intersecting the base region (32), the N well region (22) and the P well region (20). An insulating film is formed on the inner surface of the trenches (40) and gate oxide is formed on the insulating film so as to substantially fill the trenches and form a gate.
    Type: Grant
    Filed: July 2, 2014
    Date of Patent: January 1, 2019
    Assignee: ECO SEMICONDUCTORS LIMITED
    Inventor: Sankara Madathil
  • Emulating a constant power load using a constant current load
    Patent number: 10168366
    Abstract: Embodiments of the present disclosure include a method, computer program product, and system for emulating a constant power (CP) electronic load (e-load) from a constant current (CC) e-load. Testing metrics may be obtained for a power source to be tested, including one or more power thresholds. Further, an initial current level for a CC e-load may be obtained. The power-draw of the CC e-load connected to the power source may be determined. The determined power-draw may be compared to at least one of the one or more of the power thresholds. In response to the power-draw not satisfying the at least one power threshold, the current level of the CC e-load may be adjusted based on the power-draw and the at least one power threshold.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: January 1, 2019
    Assignee: International Business Machines Corporation
    Inventors: Edward L. Blackwell, Adrian P. Glover, David Rico
  • Semiconductor storage device comprising peripheral circuit, shielding layer, and memory cell array
    Patent number: 10170486
    Abstract: Probability of malfunction of a semiconductor storage device is reduced. A shielding layer is provided between a memory cell array (e.g., a memory cell array including a transistor formed using an oxide semiconductor material) and a peripheral circuit (e.g., a peripheral circuit including a transistor formed using a semiconductor substrate), which are stacked. With this structure, the memory cell array and the peripheral circuit can be shielded from radiation noise generated between the memory cell array and the peripheral circuit. Thus, probability of malfunction of the semiconductor storage device can be reduced.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 1, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tomoaki Atsumi, Takashi Okuda
  • Methods and apparatus providing a graded package for a semiconductor
    Patent number: 10170384
    Abstract: Methods and apparatus providing a graded package for a semiconductor are disclosed. An example apparatus includes a die; and a graded package encapsulating the die, the graded package including a material that is spatially varied from a first location of the graded package to a second location of the graded package.
    Type: Grant
    Filed: June 12, 2017
    Date of Patent: January 1, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Daniel Lee Revier, Benjamin Stassen Cook
  • Structure of GaN-based transistor and method of fabricating the same
    Patent number: 10170580
    Abstract: A GaN-based transistor device comprises a substrate; a buffer layer disposed on the substrate; a channel layer disposed on the buffer layer; a barrier layer disposed on a part of the channel layer; a passivation layer disposed on the barrier layer; wherein the barrier layer and the passivation layer comprise a first side wall and a second side wall; a barrier metal layer disposed on the passivation layer has a first opening that exposes a part of the passivation layer, and the passivation layer has a second opening located in the first opening; a gate electrode disposed on the exposed part of the barrier layer, a source electrode disposed on the channel layer covers the first side wall and a part of the barrier metal layer, and a drain electrode disposed on the channel layer covers the second side wall and another part of the barrier metal layer.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: January 1, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Kan-Hsueh Tsai, Heng-Yuan Lee
  • Transistor with improved channel mobility
    Patent number: 10164101
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to transistors with improved channel mobility and methods of manufacture. A structure includes: a curved beam structure formed from at least one stressed material; a cavity below the curved beam structure; and at least one semiconductor device on a top portion or a bottom portion of the curved beam structure whose carrier mobility is increased or decreased by a curvature of the curved beam structure.
    Type: Grant
    Filed: October 23, 2017
    Date of Patent: December 25, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Renata A. Camillo-Castillo, Anthony K. Stamper, Vibhor Jain, Mark D. Jaffe
  • Integrated circuit devices including FIN active areas with different shapes
    Patent number: 10157921
    Abstract: An integrated circuit device can include a substrate having a first area and a second area and a pair of first fin-shaped active areas each having a first shape protruding from the first area in a first direction, adjacent to each other, and extending in a straight line. A fin separation insulating film can be between the pair of first fin-shaped active areas in the first area and a second fin-shaped active area can protrude from the second area in the first direction and have a second shape that is different from the first shape, wherein respective widths of each of the pair of first fin-shaped active areas are less than a corresponding width of the second fin-shaped active area.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 18, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jae-yup Chung
  • Semiconductor packages and manufacturing method thereof
    Patent number: 10157850
    Abstract: A semiconductor package and a manufacturing method for the semiconductor package are provided. The semiconductor package has at least one die, conductive balls, and a molding compound. The at least one die and conductive balls are molded in a molding compound. Each of the conductive balls has a planar end portion and a non-planar end portion opposite to the planar end portion. A surface of the planar end portion of each of the conductive balls is substantially coplanar and levelled with a surface of the molding compound and a surface of the at least one die, and the non-planar end portion of each of the conductive balls protrudes from the molding compound.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Wei Wu, Jing-Cheng Lin, Szu-Wei Lu, Ying-Ching Shih
  • Method for checking the positioning accuracy of a machine part that is displaceable with respect to at least one axis by means of a drive and a controller
    Patent number: 10146205
    Abstract: A method which allows an operator to quickly form a clear picture with regard to the positioning accuracy of a machine part that is displaceable along an axis by means a drive controlled by a controller includes specifying with the controller nominal position values of the machine part in relation to a single axis, wherein the nominal position values are defined by a sine function; displacing the machine part with respect to the single axis in accordance with the nominal position values; determining with a measuring device actual position values of the machine part in relation to the single axis; and visualizing the actual position values of the machine part in relation to the single axis graphically in a circular representation.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: December 4, 2018
    Assignee: Siemens Aktiengesellschaft
    Inventors: Ricky Berghold, Lars Immenroth, Robert Pulawski, Johannes Welker
  • Modular adaptor for monitoring dispenser activity
    Patent number: 10146232
    Abstract: A data collection module for capturing dispense event information from an associated fluid dispenser is provided. In some embodiments, the data collection module includes a detection instrument for detecting activation of a dispenser actuator of the fluid dispenser and for generating an output indicating activation of the dispenser actuator. In some embodiments, the data collection module includes digital electronic circuitry for communicating the data to an associated external network.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: December 4, 2018
    Assignee: GOJO Industries, Inc.
    Inventor: Shelby Jay Buell
  • Method for fabricating semiconductor device
    Patent number: 10141263
    Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate; forming a first gate structure on the substrate, a first spacer around the first gate structure, and an interlayer dielectric (ILD) layer around the first spacer; performing a first etching process to remove part of the ILD layer for forming a recess; performing a second etching process to remove part of the first spacer for expanding the recess; and forming a contact plug in the recess.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 27, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Ching-Wen Hung, Jia-Rong Wu, Yi-Hui Lee, Ying-Cheng Liu, Chih-Sen Huang
  • Electrochemical clock and oscillator devices
    Patent number: 10135015
    Abstract: One embodiment provides an oscillator. The oscillator can include an organic electrochemical transistor, which comprises a channel and a dynamic gate. The channel can include one of: a conductive polymer, a conductive inorganic material, and a small-molecule material. An electrochemical potential of the dynamic gate can vary substantially periodically, thereby resulting in the organic electrochemical transistor having a drain current that varies substantially periodically.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: November 20, 2018
    Assignee: PALO ALTO RESEARCH CENTER INCORPORATED
    Inventor: Sean E. Doris
  • Light emitting element having protective layer
    Patent number: 10134954
    Abstract: A light emitting element for flip-chip mounting having a flat mounting surface which allows a decrease in the width of the streets of a wafer. In the light emitting element, the insulating member filling around the bumps and flattening the upper surface is formed with a margin of a region with a width which is equal to or larger than the width of the streets on the dividing lines, so that at the time of dividing the wafer along the dividing lines, the insulating member is not processed, which allows designing of the streets with a small width.
    Type: Grant
    Filed: September 26, 2016
    Date of Patent: November 20, 2018
    Assignee: NICHIA CORPORATION
    Inventors: Akinori Yoneda, Shinji Nakamura, Akiyoshi Kinouchi, Yoshiyuki Aihara, Hirokazu Sasa
  • Doped, metal oxide-based chemical sensors
    Patent number: 10132769
    Abstract: The present invention generally relates to doped, metal oxide-based sensors, wherein the doped-metal oxide is a monolayer, and platforms and integrated chemical sensors incorporating the same, methods of making the same, and methods of using the same.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: November 20, 2018
    Assignee: VAON, LLC
    Inventors: Vladimir Dobrokhotov, Alexander Larin
  • Display device
    Patent number: 10134775
    Abstract: By applying an AC pulse to a gate of a transistor which easily deteriorates, a shift in threshold voltage of the transistor is suppressed. However, in a case where amorphous silicon is used for a semiconductor layer of a transistor, the occurrence of a shift in threshold voltage naturally becomes a problem for a transistor which constitutes a part of circuit that generates an AC pulse. A shift in threshold voltage of a transistor which easily deteriorates and a shift in threshold voltage of a turned-on transistor are suppressed by signal input to a gate electrode of the transistor which easily deteriorates through the turned-on transistor. In other words, a structure for applying an AC pulse to a gate electrode of a transistor which easily deteriorates through a transistor to a gate electrode of which a high potential (VDD) is applied, is included.
    Type: Grant
    Filed: February 20, 2018
    Date of Patent: November 20, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Atsushi Umezaki