Patents Examined by Thomas L Dickey
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Patent number: 10833125Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.Type: GrantFiled: May 14, 2019Date of Patent: November 10, 2020Assignee: Hefei Reliance Memory LimitedInventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
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Patent number: 10825932Abstract: Provided is a thin film transistor including a substrate, a first spacer on the substrate, a second spacer on the first spacer, a light shield layer intervened between the first spacer and the second spacer, a semiconductor layer on the second spacer, and a gate electrode on the semiconductor layer, wherein the light shield layer includes a plurality of inclined surfaces against a top surface of the substrate.Type: GrantFiled: April 3, 2019Date of Patent: November 3, 2020Assignee: Electronics and Telecommunications Research InstituteInventors: Jae-Eun Pi, Seung Youl Kang, Jaehyun Moon, Seongdeok Ahn, Jongchan Lee, Chul Woong Joo, Chi-Sun Hwang
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Patent number: 10825956Abstract: A light-emitting device comprises a semiconductor layer; a pad electrode comprising a periphery disposed on the semiconductor layer; a finger electrode connected to the pad electrode, wherein the finger electrode comprises a first portion extended from the periphery of the pad electrode and a second portion connected to the first portion; and a plurality of first current blocking regions formed on the semiconductor layer, separated from the pad electrode and formed under the finger electrode, wherein one of the plurality of first current blocking regions is most close to the pad electrode and is separated from the pad electrode by a first distance, adjacent two of others of the plurality of first current blocking regions are separated from each other by a second distance, and the first distance is longer than the second distance.Type: GrantFiled: October 31, 2019Date of Patent: November 3, 2020Assignee: EPISTAR CORPORATIONInventors: Chien-Hua Chou, Tai-Chun Wang, Chih-Tsung Su, Biau-Dar Chen
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Patent number: 10818640Abstract: A method includes thinning a semiconductor substrate of a device die to reveal through-substrate vias that extend into the semiconductor substrate, and forming a first redistribution structure, which includes forming a first plurality of dielectric layers over the semiconductor substrate, and forming a first plurality of redistribution lines in the first plurality of dielectric layers. The first plurality of redistribution lines are electrically connected to the through-substrate vias. The method further includes placing a first memory die over the first redistribution structure, and forming a first plurality of metal posts over the first redistribution structure. The first plurality of metal posts are electrically connected to the first plurality of redistribution lines. The first memory die is encapsulated in a first encapsulant. A second plurality of redistribution lines are formed over, and electrically connected to, the first plurality of metal posts and the first memory die.Type: GrantFiled: April 2, 2019Date of Patent: October 27, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hua Yu, Chung-Hao Tsai, Chuei-Tang Wang
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Patent number: 10811513Abstract: A vertical tunneling field effect transistor is provided and includes: a semiconductor substrate; a first doped layer on the semiconductor substrate; vertical nanowires on the first doped layer; a second doped layer on a top of each vertical nanowire; an interlayer dielectric layer on the first doped layer, including a cavity between the adjacent vertical nanowires through the interlayer dielectric layer and exposing sidewalls of the adjacent vertical nanowires; a high-K gate dielectric layer in sidewalls and a bottom of each cavity; and a gate electrode layer on the high-K gate dielectric layer to fill each cavity.Type: GrantFiled: September 4, 2019Date of Patent: October 20, 2020Assignees: Semiconductor Manufacturing International (Shanghai) Corporation, Semiconductor Manufacturing International (Beijing) CorporationInventor: Yong Li
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Patent number: 10797123Abstract: A display panel includes a base layer having a first region and a bent second region. An inorganic layer is disposed on the base layer. A lower opening is formed within the inorganic layer and overlaps the second region. A first thin-film transistor is disposed on the inorganic layer and includes a silicon semiconductor pattern overlapping the first region. A second thin-film transistor is disposed on the inorganic layer and includes an oxide semiconductor pattern overlapping the first region. Insulating layers overlap the first and second regions. An upper opening is formed within the insulating layers. A signal line electrically connects the second thin-film transistor. An organic layer overlaps the first and second regions and is disposed in the lower and upper openings. A luminescent device is disposed on the organic layer and overlaps the first region.Type: GrantFiled: August 29, 2018Date of Patent: October 6, 2020Assignee: SAMSUNG DISPLAY CO., LTD.Inventors: Yoon-Jong Cho, Suyeon Yun, Seokje Seong, Seongjun Lee, Joonhoo Choi, Semyung Kwon, Kyunghyun Baek
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Patent number: 10796648Abstract: A light emitting assembly is described. In one embodiment, one or more light emitting diode (LED) devices and one or more microcontrollers are bonded to a same side of a substrate, with the one or more microcontrollers to switch and drive the one or more LED devices.Type: GrantFiled: July 15, 2019Date of Patent: October 6, 2020Assignee: Apple Inc.Inventors: Kapil V. Sakariya, Andreas Bibl, Kelly McGroddy
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Patent number: 10797106Abstract: A re-writeable non-volatile memory device including a re-writeable non-volatile two-terminal memory element (ME) having tantalum. The ME including a first terminal, a second terminal, a first layer of a conductive metal oxide (CMO), and a second layer in direct contact with the first layer. The second layer and the first layer being operative to store at least one-bit of data as a plurality of resistive states, and the first and second layer are electrically in series with each other and with the first and second terminals.Type: GrantFiled: May 14, 2019Date of Patent: October 6, 2020Assignee: Hefei Reliance Memory LimitedInventors: Christophe J. Chevallier, Steve Kuo-Ren Hsia, Wayne Kinney, Steven Longcor, Darrell Rinerson, John Sanchez, Philip F. S. Swab, Edmond R. Ward
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Patent number: 10777602Abstract: A pixel circuit includes a floating diffusion layer of a first conductivity-type between a drain/source of a second conductivity-type and a source/drain of the second conductivity-type. The source/drain and the drain/source touch the floating diffusion layer. A cathode of a photoelectric converter is electrically connected to the floating diffusion layer. An anode of the photoelectric converter touches the cathode. The cathode is of the first conductivity-type and the anode is of the second conductivity-type.Type: GrantFiled: May 13, 2019Date of Patent: September 15, 2020Assignee: Sony Semiconductor Solutions CorporationInventor: Yorito Sakano
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Patent number: 10777555Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.Type: GrantFiled: July 16, 2019Date of Patent: September 15, 2020Assignee: International Business Machines CorporationInventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
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Patent number: 10777627Abstract: The present disclosure provides an organic light emitting display substrate and a method for manufacturing the same. The organic light emitting display substrate includes a substrate, and a drive transistor and an organic light emitting diode disposed on the substrate. In a direction away from the substrate, the organic light emitting diode successively includes: a first reflective electrode, an organic light emitting layer, and a second reflective electrode. A drain of the drive transistor is electrically coupled to the first reflective electrode. The organic light emitting display substrate further includes a light guide layer. One side surface of the light guide layer is the light incident surface. The light incident surface is disposed opposite to the light outgoing surface of the organic light emitting diode so that the light emitted from the light outgoing surface enters the light guide layer.Type: GrantFiled: June 26, 2019Date of Patent: September 15, 2020Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventors: Zhen Song, Guoying Wang
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Patent number: 10777718Abstract: A display device and a method for packaging the display device are disclosed. The display device includes an optical module including multiple light-emitting units disposed apart from one another and a first plastic layer. Each light-emitting unit includes at least three LEDs, and the first plastic layer fills the gaps between the light-emitting units. The display device further includes a driver IC including a second plastic layer, driving chips, through-holes, a first structure and a second structure. The second plastic layer fills the gaps between the driving chips, and the second plastic layer has a third layer. The through-holes penetrate through the second plastic layer along a thickness direction of the through-holes and are filled with a conductive material. The first structure is electrically connected to the driving chips and to the conductive material in the through-holes. The second structure is electrically connected to the conductive material in the through-holes.Type: GrantFiled: March 14, 2019Date of Patent: September 15, 2020Assignee: INNO-PACH TECHNOLOGY PTE LTD.Inventors: Deze Yu, Wanning Zhang
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Patent number: 10777562Abstract: A method used in forming integrated circuitry comprises forming a plurality of conductive vias comprising conductive material. The conductive vias are spaced relative one another by intermediate material. A discontinuous material is formed atop the conductive material of the vias and atop the intermediate material that is between the vias. Metal material is formed atop, directly against, and between the discontinuous material and atop and directly against the conductive material of the vias. The metal material is of different composition from that of the discontinuous material and is above the intermediate material that is between the vias. The metal material with discontinuous material there-below is formed to comprise a conductive line that is atop the intermediate material that is between the vias and is directly against individual of the vias. Structures independent of method are disclosed.Type: GrantFiled: March 14, 2019Date of Patent: September 15, 2020Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, John A. Smythe
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Patent number: 10770333Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: GrantFiled: March 5, 2019Date of Patent: September 8, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.
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Patent number: 10770332Abstract: Methods of manufacturing semiconductor packages. Implementations may include: providing a substrate with a first side, a second side, and a thickness; forming a plurality of pads on the first side of the substrate; and applying die attach material to the plurality of pads. The method may include bonding a wafer including a plurality of semiconductor die to the substrate at one or more die pads included in each die. The method may also include singulating the plurality of semiconductor die, overmolding the plurality of semiconductor die and the first side of the substrate with an overmold material, and removing the substrate to expose the plurality of pads and to form a plurality of semiconductor packages coupled together through the overmold material. The method also may include singulating the plurality of semiconductor packages to separate them.Type: GrantFiled: March 5, 2019Date of Patent: September 8, 2020Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLCInventors: Darrell D. Truhitte, James P. Letterman, Jr.
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Patent number: 10763356Abstract: An embodiment relates to a device comprising a unit cell on a SiC substrate, the unit cell comprising a first well region, a source region, a plug region, and a well trench, wherein the well trench has a depth that is less than that of the first well region. Additional embodiments relate to the device having a second well region, wherein the second well region has a depth that is equal to or deeper than the first well region and the second well region is located under and around the source region.Type: GrantFiled: April 3, 2019Date of Patent: September 1, 2020Assignee: GeneSiC Semiconductor Inc.Inventors: Siddarth Sundaresan, Ranbir Singh, Jaehoon Park, Stoyan Jeliazkov
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Patent number: 10756041Abstract: A finned contact of an IC device may be utilized to electrically connect the IC device to external circuitry. The finned contact may be fabricated by forming a base upon the IC device and subsequently forming two or more fins upon the base. Each fin may be formed of the same and/or different material(s) as the base. Each fin may include layer(s) of one or materials. The fins may be located upon the base inset from the sidewall(s) of the base. The fins may be arranged as separated ring portions that are concentric with the base. The fins may drive current into the external circuitry connected thereto. Solder may be drawn towards the center of the base within an inner void that is internal to the fins, thereby limiting the likelihood of solder bridging with a neighboring contact.Type: GrantFiled: March 14, 2019Date of Patent: August 25, 2020Assignee: International Business Machines CorporationInventors: Charles L. Arvin, Brian M. Erwin, Clement J. Fortin, Chris Muzzy
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Patent number: 10755917Abstract: A nitrogen plasma treatment is used on an adhesion layer of a contact plug. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the adhesion layer. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the adhesion layer. A nitrogen plasma treatment is used on an opening in an insulating layer. As a result of the nitrogen plasma treatment, nitrogen is incorporated into the insulating layer at the opening. When a contact plug is deposited in the opening, an interlayer of a metal nitride is formed between the contact plug and the insulating layer.Type: GrantFiled: November 1, 2018Date of Patent: August 25, 2020Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yi Chen, Wei-Yip Loh, Hung-Hsu Chen, Chih-Wei Chang
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Patent number: 10741652Abstract: A method is presented for forming a wrap-around-contact. The method includes forming a bottom source/drain region adjacent a plurality of fins, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, and for forming top spacers adjacent the top portions of the plurality of fins. The method further includes disposing a sacrificial liner adjacent the encapsulation layers, recessing the top spacers, forming top source/drain regions over the top portions of the plurality of fins, removing the sacrificial liner to create trenches adjacent the top source/drain regions, and depositing a metal liner within the trenches and over the top source/drain regions such that the wrap-around-contact is defined to cover an upper area of the top source/drain regions.Type: GrantFiled: September 13, 2019Date of Patent: August 11, 2020Assignee: International Business Machines CorporationInventors: Choonghyun Lee, Christopher J. Waskiewicz, Alexander Reznicek, Hemanth Jagannathan
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Patent number: 10739027Abstract: A system and method for monitoring a heating, ventilation, or air conditioning (HVAC) system of a building is provided. A monitoring server, located remotely from the building, is configured to receive power consumption data and control signal data from a monitoring device at the building and to receive energy pricing data from a customer device associated with the HVAC system or a database that stores energy pricing data. The monitoring server is configured to determine energy cost data for segments of a selected time period based on the power consumption data, the control signal data, and the energy pricing data. The monitoring server is also configured to communicate the energy cost data to the customer device for display on the customer device.Type: GrantFiled: June 22, 2016Date of Patent: August 11, 2020Assignee: Emerson Electric Co.Inventors: Priotomo Abiprojo, Jacob Nielson