Patents Examined by Thomas L Dickey
  • Patent number: 10644149
    Abstract: Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a laterally-diffused metal-oxide-semiconductor device. A fin projects from a substrate, a channel region and a drain extension are arranged in a first section of the fin and the substrate beneath the first section of the fin, a source region is arranged in the first section of the fin, a drain region is arranged in a second section of the fin and the substrate beneath the second section of the fin, and a gate structure is arranged over the channel region. The drain region and the source region have an opposite conductivity type from the channel region. A trench isolation region is arranged in the fin between the first section of the fin and the second section of the fin. A dummy gate is arranged over a portion of the second section of the fin.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: May 5, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jagar Singh, Jerome Ciavatti
  • Patent number: 10636886
    Abstract: A semiconductor device includes a first fin type pattern and a second fin type pattern, which are isolated from each other by an isolating trench, and extend in a first direction on a substrate, respectively, a third fin type pattern which is spaced apart from the first fin type pattern and the second fin type pattern in a second direction and extends in the first direction, a field insulation film on a part of sidewalls of the first to third fin type patterns, a device isolation structure, which extends in the second direction, and is in the isolating trench, a gate insulation support, which extends in the first direction on the field insulation film between the first fin type pattern and the third fin type pattern, a gate structure, which intersects the third fin type pattern, extends in the second direction, and is in contact with the gate insulation support, wherein a height from the substrate to a bottom surface of the gate structure is greater than a height from the substrate to a bottom surface of the
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: April 28, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Min Seok Jo, Jae Hyun Lee, Jong Han Lee, Hong Bae Park
  • Patent number: 10629841
    Abstract: A display panel, a method of manufacturing the display panel, and a display device are provided. The display panel includes: an electrode layer; an auxiliary electrode layer opposite to the electrode layer; and a plurality of transparent conductive particles between the electrode layer and the auxiliary electrode layer, wherein the plurality of transparent conductive particles are configured such that the electrode layer and the auxiliary electrode layer are electrically connected with each other.
    Type: Grant
    Filed: October 25, 2018
    Date of Patent: April 21, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Ameng Zhang, Xuewu Xie, Yu Ai, Shi Sun, Hao Liu, Bowen Liu, Yubao Kong
  • Patent number: 10622292
    Abstract: A substrate that includes a first substrate portion, a second substrate portion and a second dielectric layer. The first substrate portion includes a core layer having a first core surface, and a plurality of core substrate interconnects, wherein the plurality of core substrate interconnects includes a plurality of surface core substrate interconnects formed over the first surface of core layer. The second substrate portion includes a first dielectric layer having a first dielectric surface, the first dielectric surface facing the first core surface of the core layer, and a plurality of substrate interconnects, wherein the plurality of substrate interconnects includes a plurality of interconnects formed over the first dielectric surface. The second dielectric layer is formed between the first substrate portion and the second substrate portion such that the plurality of surface core substrate interconnects and the plurality of substrate interconnects are located in the second dielectric layer.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: April 14, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Kuiwon Kang, Houssam Jomaa
  • Patent number: 10611087
    Abstract: A method of operating a Continuous Liquid Interface Printing (CLIP) printer can include receiving a set of objectives for fabrication of an object using a CLIP printer and determining an orientation for fabrication of the object based on fulfillment of the set of objectives by simulated fabrication of the object.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: April 7, 2020
    Assignee: Carbon, Inc.
    Inventors: Roy Goldman, Craig B. Carlson, Abhishek Parmar
  • Patent number: 10615374
    Abstract: A display unit of the present disclosure includes: a plurality of pixels that are disposed in a regular manner; a plurality of first openings that are provided in each of the plurality of pixels; and one or more second openings that are provided in at least a portion of a peripheral edge of each of the plurality of pixels that are disposed in a regular manner.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: April 7, 2020
    Assignee: Sony Corporation
    Inventors: Kazuma Teramoto, Takahide Ishii, Kaoru Abe
  • Patent number: 10608120
    Abstract: A multi-channel thin film transistor (“TFT”) includes: a gate electrode; a semiconductor including a first channel area, which operates within a first driving range and has a first threshold voltage, and a second channel area which operates within a second driving range smaller than the first driving range and has a second threshold voltage, where an absolute value of the second threshold voltage is greater than an absolute value of the first threshold voltage; a first electrode connected to an end of the semiconductor; and a second electrode connected to another end of the semiconductor.
    Type: Grant
    Filed: January 22, 2019
    Date of Patent: March 31, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventor: Hwangsup Shin
  • Patent number: 10607938
    Abstract: Devices and methods are provided for fabricating monolithic three-dimensional semiconductor integrated circuit devices which include power distribution networks that are implemented with power distribution planes disposed below a stack of device tiers, in between device tiers, and/or above the device tiers to distribute positive and negative power supply voltage to field-effect transistor devices of the device tiers.
    Type: Grant
    Filed: October 26, 2018
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Joshua M. Rubin, Terence B. Hook
  • Patent number: 10600718
    Abstract: This invention minimizes the thermal resistance and maximizes the power density of a power transistor by mounting the transistor in flip-chip fashion on a heat sink/heat spreader and conducting the heat from the active semiconductor layer through the heat sink/heat spreader (as opposed to through the low conductivity substrate). Illustratively, the semiconductor device package comprises: a high electron mobility transistor (HEMT) formed in a layer of Gallium Nitride (GaN) having a first major surface; at least one metal contact pad making thermal contact with the layer of GaN on its first major surface; a heat sink/heat spreader in electrical and thermal contact with the contact pad(s) on the first surface; and a substrate on which the heat sink is mounted.
    Type: Grant
    Filed: December 2, 2015
    Date of Patent: March 24, 2020
    Assignee: II-VI Delaware, Inc.
    Inventor: Kenneth Sean Ozard
  • Patent number: 10593908
    Abstract: The present application relates to an encapsulation film, a method of manufacturing the same, an organic electronic device including the same, and a method of manufacturing the organic electronic device using the same. The present application provides an encapsulation film which can be formed to have a structure in which moisture or oxygen flowing from the outside into an organic electronic device can be effectively blocked, has excellent handling properties and processability, and also has excellent bonding properties with an organic electronic element and durability.
    Type: Grant
    Filed: April 12, 2017
    Date of Patent: March 17, 2020
    Assignee: LG CHEM, LTD.
    Inventors: Jung Ok Moon, Hyun Jee Yoo, Hyun Suk Kim, Jung Woo Lee, Se Woo Yang
  • Patent number: 10586924
    Abstract: Subject matter herein disclosed relates to a method for the manufacture of a switching device comprising a correlated electron material. In embodiments, processes are described which may be useful for avoiding a resistive layer which tends to form between the correlated electron material and a conductive substrate and/or overlay.
    Type: Grant
    Filed: August 22, 2016
    Date of Patent: March 10, 2020
    Assignee: ARM Ltd.
    Inventors: Kimberly Gay Reid, Lucian Shifren, Carlos Alberto Paz de Araujo, Jolanta Celinska
  • Patent number: 10581029
    Abstract: The present disclosure provides a method for manufacturing an organic electroluminescence device, including steps of: adjusting a grating period of a periodic grating structure in such a manner that a wavelength of an emergent light beam caused by SP-coupling is within a predetermined range of a light-emission peak of the organic electroluminescence device; and forming the periodic grating structure in the organic electroluminescence device in accordance with the obtained grating period by adjustment.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: March 3, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Jun Wang, Ce Zhao, Dongfang Wang, Bin Zhou
  • Patent number: 10578552
    Abstract: A scattering tomography method includes: radiating waves to an object from transmitting antenna elements arranged on a curved surface; receiving scattered waves by receiving antenna elements arranged on the curved surface; and reconstructing an image relating to the information on the interior of the object from scattered wave data representing the scattered waves received by the receiving antenna elements, and in the reconstructing, a function ? for reconstructing the image relating to the information on the interior of the object is set in advance, an equation which a fundamental scattered function satisfies is constructed, a visualization function ? that is obtained by solving the equation is derived from the scattered wave data, and the image relating to the information on the interior of the object is reconstructed using the visualization function.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: March 3, 2020
    Assignees: INTEGRAL GEOMETRY SCIENCE INC., KENJIRO KIMURA
    Inventors: Kenjiro Kimura, Noriaki Kimura
  • Patent number: 10580793
    Abstract: In a method of manufacturing a semiconductor device, the method includes: forming a stack structure; forming a channel layer penetrating the stack structure; forming a first dielectric layer in the channel layer; forming a second dielectric layer in the first dielectric layer; forming an opening by selectively etching the first dielectric layer; selectively etching the second dielectric layer exposed through the opening; and forming a pad in the opening.
    Type: Grant
    Filed: October 4, 2018
    Date of Patent: March 3, 2020
    Assignee: SK hynix Inc.
    Inventors: Ki Hong Lee, Seung Wook Ryu
  • Patent number: 10580842
    Abstract: A first electrode (110) has optical transparency, and a second electrode (130) has light reflectivity. An organic layer (120) is located between the first electrode (110) and the second electrode (130). Light-transmitting regions (a second region (104) and a third region (106)) are located between a plurality of light-emitting units (140). An insulating film (150) defines the light-emitting units (140) and includes tapers (152, 154). A sealing member (170) covers the light-emitting units (140) and the insulating film (150). A low reflection film (190) is located on the side opposite to a substrate (100) with the second electrode (130) therebetween. The low reflection film (190) covers at least one portion of the tapers (152 and 154).
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: March 3, 2020
    Assignee: PIONEER CORPORATION
    Inventor: Takeru Okada
  • Patent number: 10571408
    Abstract: A method propagates a pulse of wave through the material to receive a set of echoes resulted from scattering the pulse by different portions of the material and simulates a propagation of the pulse in the material using a neural network to determine a simulated set of echoes. Each node in a layer of the neural network corresponds to a portion of the material and assigned a value the permittivity of the portion of the material, such that the values of the nodes at locations of the portions form the image of the distribution of the permittivity of the material. The connection between two layers in the neural network models a scattering event. The method updates the values of the nodes by reducing an error between the received set of echoes and the simulated set of echoes to produce an image of the distribution of the permittivity of the material.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: February 25, 2020
    Assignee: Mitsubishi Electric Research Laboratories, Inc.
    Inventors: Ulugbek Kamilov, Dehong Liu, Hassan Mansour, Petros T. Boufounos
  • Patent number: 10573648
    Abstract: A method for manufacturing a semiconductor device comprises forming a bottom source/drain region on a semiconductor substrate, forming a channel region extending vertically from the bottom source/drain region, growing a top source/drain region from an upper portion of the channel region, and growing a gate region from a lower portion of the channel region under the upper portion, wherein the gate region is on more than one side of the channel region.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: February 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Karthik Balakrishnan, Bahman Hekmatshoartabari, Alexander Reznicek, Jeng-Bang Yau
  • Patent number: 10566569
    Abstract: A light emitting device having a structure in which oxygen and moisture are prevented from reaching light emitting elements, and a method of manufacturing the same, are provided. Further, the light emitting elements are sealed by using a small number of process steps, without enclosing a drying agent. The present invention has a top surface emission structure. A substrate on which the light emitting elements are formed is bonded to a transparent sealing substrate. The structure is one in which a transparent second sealing material covers the entire surface of a pixel region when bonding the two substrates, and a first sealing material (having a higher viscosity than the second sealing material), which contains a gap material (filler, fine particles, or the like) for protecting a gap between the two substrates, surrounds the pixel region. The two substrates are sealed by the first sealing material and the second sealing material.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: February 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takeshi Nishi, Yasuo Nakamura
  • Patent number: 10563252
    Abstract: The present invention is a biosensor apparatus that includes a substrate, a source on one side of the substrate, a drain spaced from the source, a conducting channel between the source and the drain, an insulator region, and receptors on a gate region for receiving target material. The receptors are contacted for changing current flow between the source and the drain. The source and the drain are relatively wide compared to length between the source and the drain through the conducting channel.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: February 18, 2020
    Assignee: UNIVERSITY OF HAWAII
    Inventor: James Holm-Kennedy
  • Patent number: 10553729
    Abstract: According to an aspect of the present invention, there is provided a nonvolatile semiconductor storage device including: a semiconductor substrate; a source region and a drain region that are formed in the semiconductor substrate so as to be separated from each other and so as to define a channel region therebetween; a tunnel insulating film that is formed on the channel region; an insulative charge storage film that is formed on the tunnel insulating film; a conductive charge storage film that is formed on the insulative charge storage film so as to be shorter than the insulative charge storage film in a channel direction; an interlayer insulating film that is formed on the conductive charge storage film; and a gate electrode that is formed on the interlayer insulating film.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: February 4, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Takamitsu Ishihara, Koichi Muraoka