Abstract: A light emitting diode package includes a light emitting diode chip, a light conversion layer covering the light emitting diode chip, a reflecting layer surrounding the light emitting diode chip. The light emitting chip has a light output top surface, a first electrode and a second electrode. The first electrode and the second electrode are opposite to the light output top surface. The light emitting diode package further includes a supporting layer made of metal material. The supporting layer is mounted on a bottom surface of the reflecting layer facing away from the light output top surface and surrounds the light emitting chip and the light conversion layer.

Abstract: A method is presented for forming a wrap-around-contact. The method includes forming a bottom source/drain region adjacent a plurality of fins, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, and for forming top spacers adjacent the top portions of the plurality of fins. The method further includes disposing a sacrificial liner adjacent the encapsulation layers, recessing the top spacers, forming top source/drain regions over the top portions of the plurality of fins, removing the sacrificial liner to create trenches adjacent the top source/drain regions, and depositing a metal liner within the trenches and over the top source/drain regions such that the wrap-around-contact is defined to cover an upper area of the top source/drain regions.

Abstract: This light-receiving element includes: a substrate; a photoelectric conversion layer that is provided on the substrate and includes a first compound semiconductor, and absorbs a wavelength in an infrared region to generate electric charges; a semiconductor layer that is provided on the photoelectric conversion layer and includes a second compound semiconductor, and has an opening in a selective region; and an electrode that buries the opening of the semiconductor layer and is electrically coupled to the photoelectric conversion layer.

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

Abstract: A FinFET device includes a substrate, first and second fins, first and second gates and first and second epitaxial layers. The substrate has a first region and a second region. The first and second fins are on the substrate respectively in the first and second regions. In an embodiment, the number of the first fins is different from the number of the second fins. The first and second gates are on the substrate and respectively across the first and second fins. The first epitaxial layers are disposed in first recesses of the first fins adjacent to the first gate. The second epitaxial layers are disposed in second recesses of the second fins adjacent to the second gate. In an embodiment, the maximum width of the first epitaxial layers is L1, the maximum width of the second epitaxial layers is L2, and (L2?L1)/L1 is equal to or less than about 1%.

Abstract: An array substrate, manufacturing method thereof, and display device. The array substrate comprises a subpixel unit, and the subpixel unit comprises: a first transparent common electrode a pixel electrode disposed over and insulated from the first transparent common electrode, wherein an orthographic projection of the first transparent common electrode on a surface where the pixel electrode is located has an overlapping portion with the pixel electrode; and a second transparent common electrode disposed over and insulated from the pixel electrode.

Abstract: A method of manufacturing an organic light emitting display device, including: forming a first film of an organic material, and having first and second surfaces facing each other and a third surface perpendicular to the first and second surfaces; forming a second film on the first film to cover the second and third surfaces of the first film; forming an organic light emitting unit on the second film; forming a third film on the second film to cover the organic light emitting unit; forming a fourth film of an organic material on the third film and having fourth and fifth surfaces facing each other and the fifth surface facing the third film; combining the second support substrate and the first support substrate such that the fifth surface faces the third film; detaching the second support substrate from the fourth surface; and detaching the first support substrate from the first surface.

Abstract: An image sensor includes a photoelectric conversion element and a charge storage node coupled to the photoelectric conversion element. The charge storage node may store photocharges generated in the photoelectric conversion element. The charge storage node may include a floating diffusion region in a semiconductor substrate, a barrier dopant region on the floating diffusion region in the semiconductor substrate, and a charge drain region on the barrier dopant region in the semiconductor substrate, where the semiconductor substrate is associated with a first conductivity type, the floating diffusion region is associated with a second conductivity type, the barrier dopant region is associated with the first conductivity type, and the charge drain region is associated with the second conductivity type.

Abstract: A semiconductor device includes: an n-type drift region; a p-type base region above the drift region; a gate electrode disposed inside a trench above the drift region with a gate insulating film between the trench and the gate electrode; an n-type source region above the base region; a source electrode connected to the source region; an n-type drain region below the drift region; a drain electrode connected to the drain region; a p-type protective layer that is disposed inside the drift region and below the trench, the protective layer protruding beyond a trench width of the trench; and a p-type conductive path formation layer that is disposed between the protective layer and a bottom of the trench and protrudes beyond the trench width, the conductive path formation layer having protruding regions of which an impurity concentration therein is set so that an inversion layer is formed during ON.

Abstract: A high TCR tungsten resistor on a reverse biased Schottky diode. A high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A high TCR tungsten resistor embedded in a intermetal dielectric layer above a lower interconnect layer and below an upper interconnect layer. A method of forming a high TCR tungsten resistor on a reverse biased Schottky diode. A method of forming high TCR tungsten resistor on an unsilicided polysilicon platform geometry. A method of forming high TCR tungsten resistor between two parallel polysilicon leads on remaining contact etch stop dielectric. A method of forming high TCR tungsten resistor embedded in a inter metal dielectric layer above a lower interconnect layer and below an upper interconnect layer.

Abstract: Methods and devices integrating circuitry including both III-N (e.g., GaN) transistors and Si-based (e.g., Si or SiGe) transistors. In some monolithic wafer-level integration embodiments, a silicon-on-insulator (SOI) substrate is employed as an epitaxial platform providing a first silicon surface advantageous for seeding an epitaxial III-N semiconductor stack upon which III-N transistors (e.g., III-N HFETs) are formed, and a second silicon surface advantageous for seeding an epitaxial raised silicon upon which Si-based transistors (e.g., Si FETs) are formed. In some heterogeneous wafer-level integration embodiments, an SOI substrate is employed for a layer transfer of silicon suitable for fabricating the Si-based transistors onto another substrate upon which III-N transistors have been formed. In some such embodiments, the silicon layer transfer is stacked upon a planar interlayer dielectric (ILD) disposed over one or more metallization level interconnecting a plurality of III-N HFETs into HFET circuitry.

Abstract: A semiconductor structure includes a substrate. The substrate includes a plurality of function regions and a plurality of heat-dissipation regions. Each heat-dissipation region is adjacent to at least one function region. The semiconductor structure also includes a plurality of active fin structures, protruding from the substrate of the plurality of function regions; a plurality of channel layers, each formed on an active fin structure; and a plurality of heat-dissipation fin structures, protruding from the substrate of the plurality of heat-dissipation regions.

Abstract: A VTFET device and fabrication method is provided. The method includes: forming a first doped layer on a semiconductor substrate. Vertical nanowires are formed on the first doped layer. Dummy gate layers are formed on the first doped layer, and a first interlayer dielectric layer is formed on a top surface of the first doped layer exposed by dummy gate layers. Grooves are formed in the first interlayer dielectric layer, by removing a portion of the first interlayer dielectric layer and removing a partial thickness of the vertical nanowires. A second doped layer is formed in each groove. Openings are formed by etching the first interlayer dielectric layer between adjacent vertical nanowires, to expose the dummy gate layers. The dummy gate layers are removed through the openings to form cavities and each cavity includes the opening and a space provided by the removed dummy gate layers.

Abstract: A white light emitting device includes a substrate, a first light emitting diode configured to emit first blue light having a peak intensity at a wavelength within the range of 445 nm to 455 nm, a second light emitting diode configured to emit second blue light having a peak intensity at a wavelength within the range of 465 nm to 495 nm, and a wavelength conversion unit configured to convert portions of the first blue light and the second blue light, and to provide white light formed by a combination of the converted portions of the first blue light and the second blue light with unconverted portions of the first blue light and the second blue light. The wavelength conversion unit includes a first wavelength conversion material configured to emit first light having a peak intensity at a wavelength within the range of 520 nm to 560 nm, and a second wavelength conversion material configured to emit second light having a peak intensity at a wavelength within the range of 600 nm to 645 nm.

Abstract: A system and/or method for utilizing microelectromechanical systems (MEMS) switching technology to operate MEMS sensors. As a non-limiting example, a MEMS switch may be utilized to control DC and/or AC bias applied to MEMS sensor structures. Also for example, one or more MEMS switches may be utilized to provide drive signals to MEMS sensors (e.g., to provide a drive signal to a MEMS gyroscope).

Abstract: System, method, and computer program product to select a desired portion of a subject to receive a radiation dose, including: determining a plurality of Pareto points on a Pareto surface (PS); selecting a first reference point (p1) on a back side of an assumed Pareto surface (PS?) and first direction (q1) emerging therefrom towards PS? from behind; selecting a first starting adjustment (x10) and iteratively developing forward a minimum criterion in steps until a final adjustment (x11) is reached that still is implementable in the radiation apparatus; stopping the forward development, thereby determining x11 represented by a final front point (y11) as a real Pareto point of PS?; and along q1, dismissing undetermined portions of the objective space in front of and behind y11 as not containing parts of the PS, and continuing with other remaining more determined portions that are assumed to each contain a part of PS?.

Abstract: An array substrate and an organic light-emitting diode (OLED) display device are provided. The array substrate includes: a thin-film transistor (TFT) substrate and a plurality of driver integrated circuits (ICs), the TFT substrate includes a substrate and a plurality of pixel units disposed on one surface of the substrate; and the plurality of driver ICs are disposed on the other surface of the substrate and configured to transmit signals to the pixel units. In the array substrate, the driver ICs can have enough driving capability to drive the pixel units, so that the image brightness displayed by the OLED display device can become more uniform.

Abstract: A stretchable display panel, a manufacturing method of the stretchable display panel and a stretchable display apparatus are provided. The manufacturing method of the stretchable display panel includes: providing a first substrate; defining a plurality of pixel regions and a plurality of stretchable regions in the first substrate; each stretchable region being located between two adjacent pixel regions; forming a pixel device in each pixel region, and forming a conducting wire connecting two adjacent pixel regions in each stretchable region; wherein a length of the conducting wire is greater than a distance between two adjacent pixel regions. In this way, the stretchable display panel may achieve a great amount of deformation, and the display panel can be bent conveniently.

Abstract: One embodiment provides electronic device, which can include at least two organic electrochemical transistors (OECTs). A respective OECT includes a conductive channel, a gate electrically coupled to the conductive channel via a first electrolyte, and source and drain electrodes separated from each other by the conductive channel. The electrochemical potentials of redox-couples of the at least two organic electrochemical transistors are different, thereby resulting in the at least two organic electrochemical transistors having different threshold voltages. An alternative embodiment can provide an organic electrochemical transistor (OECT). The OECT can include a conductive channel, a gate electrically coupled to the conductive channel via a first electrolyte, and source and drain electrodes separated from each other by the conductive channel. The gate can include a conductive current collector and at least one redox-couple.

Abstract: Variable resistance memory devices are provided. A variable resistance memory device includes a memory cell that includes a switching device and a resistance sensing element that is connected in series with the switching device. The variable resistance memory device includes a word line that extends in a first direction and that is connected to a gate of the switching device. Moreover, the variable resistance memory device includes a plurality of bit lines extending in a second direction. A first connection node of a first bit line among the plurality of bit lines is electrically connected to the resistance sensing element. A second connection node of a second bit line, among the plurality of bit lines, adjacent the first bit line is electrically connected to the switching device.