Patents Examined by Thomas Pham
  • Patent number: 10090160
    Abstract: There is provided dry etching apparatus including a stage on which a wafer is placed, an antenna electrode, a high frequency power supply, a shower plate, and an RF bias power supply. Further, a bias path controller is provided on the side of the antenna electrode. The bias path controller resonates in series with the static reactance formed by the shower plate with respect to the frequency of the RF bias. Then, the bias path controller changes and grounds the impedance by the variable inductive reactance. With this mechanism, highly uniform etching can be achieved even if a shower plate of quartz is used for corrosive gases.
    Type: Grant
    Filed: January 21, 2016
    Date of Patent: October 2, 2018
    Inventors: Masahito Mori, Masaru Izawa, Katsushi Yagi
  • Patent number: 10062578
    Abstract: A method of selectively etching a metal-containing film from a substrate comprising a metal-containing layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber, and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions, and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the metal-containing layer at a higher etch rate than the reactive gas etches the silicon oxide layer.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: August 28, 2018
    Assignee: Applied Materials, Inc.
    Inventors: Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
  • Patent number: 10049903
    Abstract: Methods of manufacturing a heater are provided that generally include forming a laminate having a dielectric layer, a first double-sided adhesive dielectric layer, and a conductive layer. Next, a circuit pattern is created into the conductive layer, and then the circuit pattern is covered with a second double-sided adhesive dielectric layer. The second double-sided adhesive dielectric layer is covered with a sacrificial layer, and then the heater is formed, the heater comprising the dielectric layer, the first double-sided adhesive dielectric layer, the conductive layer, and the second double-sided adhesive dielectric layer. Subsequently, the sacrificial layer is removed.
    Type: Grant
    Filed: August 30, 2012
    Date of Patent: August 14, 2018
    Assignee: Watlow Electric Manufacturing Company
    Inventors: Kevin Ptasienski, Allen Norman Boldt, Janet Lea Smith, Cal Thomas Swanson, Mohammad Nosrati, Kevin Robert Smith
  • Patent number: 10037869
    Abstract: A plasma processing device may include a plasma processing chamber, a plasma electrode assembly, a wafer stage, a plasma producing gas inlet, a plurality of vacuum ports, at least one vacuum pump, and a multi-port valve assembly. The multi-port valve assembly may comprise a movable seal plate positioned in the plasma processing chamber. The movable seal plate may comprise a transverse port sealing surface that is shaped and sized to completely overlap the plurality of vacuum ports in a closed state, to partially overlap the plurality of vacuum ports in a partially open state, and to avoid substantial overlap of the plurality of vacuum ports in an open state. The multi-port valve assembly may comprise a transverse actuator coupled to the movable seal plate and a sealing actuator coupled to the movable seal plate.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: July 31, 2018
    Assignee: Lam Research Corporation
    Inventors: Daniel A. Brown, Michael C. Kellogg, Leonard J. Sharpless, Allan K. Ronne, James E. Tappan
  • Patent number: 10032631
    Abstract: A method of fabricating a mask pattern includes providing numerous masks on a substrate. A wider trench and a narrower trench are respectively defined between the mask. Subsequently, a mask material is formed to fill in the wider trench and the narrower trench. The top surface of the mask material overlapping the wider trench is lower than the top surface of the mask material overlapping the narrower trench. A photoresist layer is formed on the mask material overlapping the wider trench. Later, the mask material overlapping the narrower trench is etched while the mask material overlapping the wider trench is protected by the photoresist layer.
    Type: Grant
    Filed: May 10, 2017
    Date of Patent: July 24, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Li-Chiang Chen, Fu-Che Lee, Ming-Feng Kuo, Hsien-Shih Chu, Cheng-Yu Wang, Yu-Chen Chuang
  • Patent number: 10002804
    Abstract: Described is a method for determining an endpoint of an etch process using optical emission spectroscopy (OES) data as an input. Optical emission spectroscopy (OES) data are acquired by a spectrometer attached to a plasma etch processing tool. The acquired time-evolving spectral data are first filtered and demeaned, and thereafter transformed into transformed spectral data, or trends, using multivariate analysis such as principal components analysis, in which previously calculated principal component weights are used to accomplish the transform. A functional form incorporating multiple trends may be used to more precisely determine the endpoint of an etch process. A method for calculating principal component weights prior to actual etching, based on OES data collected from previous etch processing, is disclosed, which method facilitates rapid calculation of trends and functional forms involving multiple trends, for efficient and accurate in-line determination of etch process endpoint.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: June 19, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Yan Chen, Vi Vuong, Serguei Komarov
  • Patent number: 9972498
    Abstract: A method of fabricating a gate cap layer includes providing a substrate with an interlayer dielectric disposed thereon, wherein a recess is disposed in the interlayer dielectric and a metal gate fills in a lower portion of the recess. Later, a cap material layer is formed to cover the interlayer dielectric and fill in an upper portion of the recess. After that, a first sacrifice layer and a second sacrifice layer are formed in sequence to cover the cap material layer. The first sacrifice layer has a composition different from a composition of the cap material layer. The second sacrifice layer has a composition the same as the composition of the cap material layer. Next, a chemical mechanical polishing process is preformed to remove the second sacrifice layer, the first sacrifice layer and the cap material layer above a top surface of the interlayer dielectric.
    Type: Grant
    Filed: March 27, 2016
    Date of Patent: May 15, 2018
    Inventors: Fu-Shou Tsai, Yu-Ting Li, Chih-Hsun Lin, Li-Chieh Hsu, Yi-Liang Liu, Po-Cheng Huang, Kun-Ju Li, Wen-Chin Lin
  • Patent number: 9944827
    Abstract: The CMP polishing solution of the invention comprises (A) a metal corrosion inhibitor containing a compound with a 1,2,3-triazolo[4,5-b]pyridine skeleton, (B) an abrasive grain having a positive zeta potential in the CMP polishing solution, (C) a metal oxide solubilizer and (D) an oxidizing agent. The polishing method of the invention comprises a first polishing step in which the conductive substance layer of a substrate comprising an interlayer insulating filth having an elevated section and a trench at the surface, a barrier layer formed following the surface of the interlayer insulating film and the conductive substance layer formed covering the barrier layer, is polished to expose the barrier layer located on the elevated section of the interlayer insulating film, and a second polishing step in which the barrier layer exposed in the first polishing step is polished using the CMP polishing solution to expose the elevated section of the interlayer insulating film.
    Type: Grant
    Filed: June 29, 2011
    Date of Patent: April 17, 2018
    Inventors: Kouji Mishima, Takafumi Sakurada, Tomokazu Shimada
  • Patent number: 9909214
    Abstract: A method for depositing a dielectric film in a trench by plasma-enhanced atomic layer deposition (PEALD) includes depositing a dielectric film in a trench of a substrate by PEALD under conditions wherein the wet etch rate of the depositing film on a top surface of the substrate is substantially equivalent to or higher than the wet etch rate of the depositing film at a sidewall of the trench, wherein a precursor fed into the reaction space has —N(CH3)2 as a functional group.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: March 6, 2018
    Assignee: ASM IP Holding B.V.
    Inventor: Hidemi Suemori
  • Patent number: 9887083
    Abstract: A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO2 is deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuO2 and the dielectric metal oxide layer are annealed at a temperature below 500° C. The RuO2 in physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: February 6, 2018
    Assignee: Micron Technology, Inc.
    Inventors: Vassil N. Antonov, Vishwanath Bhat
  • Patent number: 9868641
    Abstract: Implementations and techniques for conforming a layer of graphene to a target substrate are generally disclosed.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: January 16, 2018
    Inventor: Thomas A. Yager
  • Patent number: 9823567
    Abstract: A manufacturing method of a mask plate for shielding during sealant-curing includes: forming a negative photoresist light-shielding material layer on a transparent substrate; with a color-filter mask plate set, exposing the substrate formed with the negative photoresist light-shielding material layer; developing the substrate after exposing to form the pattern of the mask plate. The method does not require separate fabrication of a mask plate, thereby significantly reducing the manufacturing costs of the mask plate for shielding during sealant-curing.
    Type: Grant
    Filed: June 14, 2013
    Date of Patent: November 21, 2017
    Inventors: Yong Liu, Xiaohe Li, Hongmin Li, Xianjie Shao, Qinghua Jiang
  • Patent number: 9818930
    Abstract: A support structure includes an internal cavity. An elastic membrane extends to divide the internal cavity into a first chamber and a second chamber. The elastic membrane includes a nanometric-sized pin hole extending there through to interconnect the first chamber to the second chamber. The elastic membrane is formed of a first electrode film and a second electrode film separated by a piezo insulating film. Electrical connection leads are provided to support application of a bias current to the first and second electrode films of the elastic membrane. In response to an applied bias current, the elastic membrane deforms by bending in a direction towards one of the first and second chambers so as to produce an increase in a diameter of the pin hole.
    Type: Grant
    Filed: November 11, 2015
    Date of Patent: November 14, 2017
    Inventor: John Hongguang Zhang
  • Patent number: 9809027
    Abstract: A method of manufacturing a structure includes (1) positioning a first resin layer provided on a first supporting member on a substrate having a through hole, with the first resin layer facing toward the substrate, and releasing the first supporting member from the first resin layer; and (2) positioning a second resin layer provided on a second supporting member on the first resin layer from which the first supporting member has been released, with the second resin layer facing toward the first resin layer, and releasing the second supporting member from the second resin layer. A first resin layer portion that is above the through hole is removed before or simultaneously with the releasing of the first supporting member.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: November 7, 2017
    Inventors: Keiji Matsumoto, Jun Yamamuro, Kazuhiro Asai, Kunihito Uohashi, Seiichiro Yaginuma, Masahisa Watanabe, Koji Sasaki, Ryotaro Murakami, Kenji Fujii
  • Patent number: 9804122
    Abstract: A technique relates to manufacturing a nanogap. An oxide layer is disposed on top of a substrate. A release layer is disposed in a pattern on top of the oxide layer. A patterned trench is etched into the oxide layer using the pattern of the release layer. A metal layer is disposed on the release layer and in the patterned trench. A polish removes the release layer, thereby removing both the release layer and a portion of the metal layer having been disposed on top of the release layer, such that the metal layer remaining includes a first metal part and a second metal part connected by a metal nanowire. The metal layer remaining is coplanar with the oxide layer. A nanochannel is formed in the oxide layer in a region of the metal nanowire. The nanogap is formed in the metal nanowire separating the first and second metal parts.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: October 31, 2017
    Inventors: Huan Hu, Michael F. Lofaro, Joshua T. Smith, Daniel J. Solis, Benjamin H. Wunsch
  • Patent number: 9779960
    Abstract: One illustrative method disclosed herein includes, among other things, forming a fin-removal masking layer comprised of a plurality of line-type features, each of which is positioned above one of the fins, and a masking material positioned at least between adjacent features of the fin-removal masking layer and above portions of an insulating material in the trenches between the fins. The method also includes performing an anisotropic etching process through the fin-removal masking layer to remove the portions of the fins to be removed.
    Type: Grant
    Filed: June 1, 2015
    Date of Patent: October 3, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Ruilong Xie, Min Gyu Sung, Catherine B. Labelle
  • Patent number: 9758382
    Abstract: Various implementations and embodiments relate to three-dimensional open cellular diamond micro-truss structures and methods.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: September 12, 2017
    Assignee: HRL Laboratories, LLC
    Inventors: Christopher S. Roper, William B. Barvosa-Carter, Alan J. Jacobsen, Tobias Schaedler
  • Patent number: 9732428
    Abstract: The invention relates to compositions and methods that are useful in etching a metal surface. In particular, the invention relates to novel acid compositions and methods of using such compositions in etching a metal surface, preferably an aluminum surface prior to anodizing to dissolve impurities, imperfections, scale, and oxide. The compositions are effective in maintaining their etching capacity and in removing smut produced by the etching of a surface as well as in general cleaning.
    Type: Grant
    Filed: March 22, 2015
    Date of Patent: August 15, 2017
    Assignee: Houghton Technical Corp.
    Inventor: Mores Basaly
  • Patent number: 9698062
    Abstract: A system and method for performing a wet etching process is disclosed. The system includes multiple processing stations accessible by a transfer device, including a measuring station to optically measure the thickness of a substrate, a controller to calculate an etch recipe for the substrate, in real time, and cause a single wafer wet etching station to etch the substrate according to the recipe. In addition, the system can measure the after etch thickness and calculate etch recipes, in real time, as a function of the final measurements of a previous substrate. The system can also include an in situ end point detection device for detecting the TSV reveal point while etching TSVs substrates. The system provides an automated solution to adjust etch recipe parameters in real time according to feedback concerning previously etched wafers and precisely control the TSV reveal height and etch duration using end point detection.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: July 4, 2017
    Inventors: Laura Mauer, Elena Lawrence, John Taddei, Ramey Youssef
  • Patent number: 9698031
    Abstract: A substrate treatment method is provided, which includes: an organic solvent replacing step of supplying an organic solvent, whereby a liquid film of the organic solvent is formed on the substrate as covering the upper surface of the substrate to replace a rinse liquid with the organic solvent; a substrate temperature increasing step of allowing the temperature of the upper surface of the substrate to reach a first temperature level higher than the boiling point of the organic solvent after the formation of the organic solvent liquid film, whereby a vapor film of the organic solvent is formed below the entire organic solvent liquid film between the organic solvent liquid film and the substrate to levitate the organic solvent liquid film above the organic solvent vapor film; and an organic solvent removing step of removing the levitated organic solvent liquid film from above the upper surface of the substrate.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: July 4, 2017
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Kenji Kobayashi, Manabu Okutani