Patents Examined by Thomas Pham
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Patent number: 9064815Abstract: A method of selectively etching a metal-containing film from a substrate comprising a metal-containing layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber, and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions, and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the metal-containing layer at a higher etch rate than the reactive gas etches the silicon oxide layer.Type: GrantFiled: March 9, 2012Date of Patent: June 23, 2015Assignee: Applied Materials, Inc.Inventors: Jingchun Zhang, Anchuan Wang, Nitin Ingle
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Patent number: 9034200Abstract: The present invention relates to a method of producing a diamond surface including the steps of providing an original diamond surface, subjecting the original diamond surface to plasma etching to remove at least 2 nm of material from the original surface and produce a plasma etched surface, the roughness Rq of the plasma etched surface at the location of the etched surface where the greatest depth of material has been removed satisfying at least one of the following conditions: Rq of the plasma etched surface is less than 1.5 times the roughness of Rq of the original surface, or Rq of the plasma etched surface is less than 1 nm.Type: GrantFiled: January 22, 2008Date of Patent: May 19, 2015Assignee: Element Six Limited Technologies LimitedInventors: Chee-Leong Lee, Erdan Gu, Geoffrey Alan Scarsbrook, Ian Friel, Martin David Dawson
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Patent number: 9034772Abstract: A method of etching a substrate by plasma via a mask having a predetermined pattern at back of a silicon layer of the substrate, a semiconductor device being formed at front of which supported by a support substrate, includes a main etching step in which plasma is generated by supplying a process gas including a mixed gas whose flow ratio of fluorine compound gas, oxygen gas and silicon fluoride gas is 2:1:1.5 or a process gas including a mixed gas in which at least the ratio of one of the oxygen gas and the silicon fluoride gas, using the fluorine compound gas as a standard, is larger than the above ratio, and the substrate is etched by the plasma; and an over etching step in which the substrate is further etched by plasma while applying a high frequency for bias whose frequency is less than or equal to 400 kHz.Type: GrantFiled: July 18, 2013Date of Patent: May 19, 2015Assignee: TOKYO ELECTRON LIMITEDInventors: Koji Maruyama, Mikio Yamamoto
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Patent number: 9023224Abstract: The present disclosure pertains to a method of forming a spacer patterning mask. The method entails: providing a substrate; depositing, on the substrate, an interface layer, a core film and a first hard mask; patterning the core film and the first hard mask to form strips; depositing a spacer patterning layer to cover the core film and the first hard mask in the intermediate pattern; planarizing the spacer patterning layer by using the first hard mask in the intermediate pattern as a stop layer; etching the planarized spacer patterning layer; dry etching the second hard mask to expose the partially-etched spacer patterning layer; dry etching the exposed spacer patterning layer to form a spacer pattern; and removing the remaining first hard mask and second hard mask and the core film to obtain the final spacer patterning mask.Type: GrantFiled: May 15, 2014Date of Patent: May 5, 2015Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventors: Xinpeng Wang, Haiyang Zhang
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Patent number: 9011706Abstract: A foraminous microstructure or film that has photonic or plasmonic properties is made by forming a structure or film composed of at least two constituent materials so that the compositional ratio of the constituent materials varies in a depth direction of the structure, and then removing one of the materials from the structure.Type: GrantFiled: December 16, 2008Date of Patent: April 21, 2015Assignee: City University of Hong KongInventors: Yang Yang Li, Zhengtao Xu, Chun Kwan Tsang
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Patent number: 9011702Abstract: One of objects is to reduce the effect caused by the volume expansion of an active material. An embodiment is a method for manufacturing an electrode for a power storage device which includes an active material over one of surfaces of a current collector. The active material is formed by forming a conductive body functioning as the current collector; forming a mixed layer including an amorphous region and a microcrystalline region over one of surfaces of the conductive body; and etching the mixed layer selectively, so that a part of or the whole of the amorphous region is removed and the microcrystalline region is exposed. Thus, the effect caused by the volume expansion of the active material is reduced.Type: GrantFiled: September 23, 2010Date of Patent: April 21, 2015Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Kazutaka Kuriki, Junpei Momo, Rie Matsubara
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Patent number: 8980753Abstract: A method for fabricating a metal gate transistor is disclosed. The method includes the steps of: providing a substrate having a first transistor region and a second transistor region; forming a first metal-oxide semiconductor (MOS) transistor on the first transistor region and a second MOS transistor on the second transistor region, in which the first MOS transistor includes a first dummy gate and the second MOS transistor comprises a second dummy gate; forming a patterned hard mask on the second MOS transistor, in which the hard mask includes at least one metal atom; and using the patterned hard mask to remove the first dummy gate of the first MOS transistor.Type: GrantFiled: September 21, 2010Date of Patent: March 17, 2015Assignee: United Mircroelectronics Corp.Inventors: Yeng-Peng Wang, Chun-Hsien Lin, Chiu-Hsien Yeh, Chin-Cheng Chien, Chan-Lon Yang
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Patent number: 8920661Abstract: A method for making a graphene/carbon nanotube composite structure includes providing a metal substrate including a first surface and a second surface opposite to the first surface, growing a graphene film on the first surface of the metal substrate by a CVD method, providing at least one carbon nanotube film structure on the graphene film, and combining the at least one carbon nanotube film structure with the graphene film, and combining the polymer layer with the at least one carbon nanotube film structure and the graphene film, and forming a plurality of stripped electrodes by etching the metal substrate from the second surface.Type: GrantFiled: November 23, 2011Date of Patent: December 30, 2014Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.Inventors: Kai-Li Jiang, Xiao-Yang Lin, Lin Xiao, Shou-Shan Fan
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Patent number: 8916053Abstract: A pattern forming method according to an embodiment includes: forming a pattern film on a first substrate, the pattern film having a concave-convex pattern, the pattern film being made of a material containing a first to-be-imprinted agent; forming a material film on a second substrate, the material film containing a second to-be-imprinted agent having a higher etching rate than an etching rate of the first to-be-imprinted agent; transferring the concave-convex pattern of the pattern film onto the material film by applying pressure between the first substrate and the second substrate, with the pattern film being positioned to face the material film, and by curing the second to-be-imprinted agent; detaching the first substrate from the pattern film; and removing the material film by etching, to leave the pattern film on the second substrate.Type: GrantFiled: June 20, 2012Date of Patent: December 23, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Yoshiaki Kawamonzen, Yasuaki Ootera, Akiko Yuzawa, Naoko Kihara, Yoshiyuki Kamata, Hiroyuki Hieda, Norikatsu Sasao, Ryosuke Yamamoto, Takeshi Okino, Tomoyuki Maeda, Takuya Shimada
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Patent number: 8883021Abstract: A method of forming of MEMS nanostructures includes a portion of a substrate is recessed to form a plurality of mesas in the substrate. Each of the plurality of mesas has a top surface and a sidewall surface. A light reflecting layer is deposited over the substrate thereby covering the top surface and the sidewall surface of each mesa. A protection layer is formed over the light reflecting layer. An ARC layer is formed over the protection layer. An opening in a photo resist layer is formed over the ARC layer over each mesa. A portion of the ARC layer, the protection layer and the light reflecting layer are removed through the opening to expose the top surface of each mesa. The photo resist layer and the ARC layer over the top surface of each mesa are removed.Type: GrantFiled: May 7, 2012Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-Hsien Chang, Chun-Ren Cheng, Yi-Shao Liu, Allen Timothy Chang, Ching-Ray Chen, Yeh-Tseng Li, Wen-Hsiang Lin
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Patent number: 8870164Abstract: A recovery process of a damaged layer and a reducing process of an oxide are performed on a substrate in which the oxide and the damaged layer from which carbon has been eliminated are formed on exposed surfaces of a Cu wiring and a SiCOH film as a low-k film, respectively. In the same processing chamber 51, a recovery process of a damaged layer 15 and a reducing process of an oxide/fluoride layer 16 are performed on a wafer W in which the damaged layer 15 from which carbon has been eliminated and the oxide/fluoride layer 16 are formed on exposed surfaces of an interlayer insulating film 4 containing SiCOH and a wiring 2 containing Cu, respectively, by consecutively supplying H2 gas and TMSDMA gas containing silicon and carbon in sequence.Type: GrantFiled: January 18, 2011Date of Patent: October 28, 2014Assignee: Tokyo Electron LimitedInventor: Wataru Shimizu
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Patent number: 8858818Abstract: The effects of knock-on oxide in a semiconductor substrate are reduced by providing a semiconductor substrate and forming a thin layer of native oxide on the semiconductor substrate. Ion implantation is performed through the native oxide layer. The native oxide layer reduces the phenomenon of knock-on oxide and oxygen concentration within the semiconductor substrate. Further reduction may be achieved by etching the surface of the semiconductor substrate in order to eliminate a concentration of oxygen at a surface of the semiconductor substrate.Type: GrantFiled: September 30, 2010Date of Patent: October 14, 2014Assignee: SuVolta, Inc.Inventors: Pushkar Ranade, Toshifumi Mori, Ken-ichi Okabe, Toshiki Miyake
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Patent number: 8815746Abstract: An apparatus and the use of such an apparatus and method for producing microcomponents with component structures are presented which are generated in a process chamber on a substrate according to the LIGA method for example and are stripped from the enclosing photoresist with the help of a cooled remote plasma source.Type: GrantFiled: August 30, 2012Date of Patent: August 26, 2014Assignee: R3T GmbH Rapid Reactive Radicals TechnologyInventor: Josef Mathuni
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Patent number: 8808553Abstract: A process for producing a liquid ejection head including a silicon substrate having a first surface and a second surface that is a surface on an opposite side to the first surface, an ejection energy generating element which is formed on a side of the first surface side and generates energy for ejecting a liquid, a cavity formed in the second surface and a liquid supply port which is formed in a bottom part of the cavity and communicates with the first surface, including, in the following order: (1) forming the cavity in the second surface of the silicon substrate by a first crystal anisotropic etching; (2) forming a chemical leading hollow in a slope of the cavity; (3) expanding the cavity by a second crystal anisotropic etching; and (4) forming the liquid supply port in a bottom face of the cavity by dry etching with the use of an ion.Type: GrantFiled: November 26, 2012Date of Patent: August 19, 2014Assignee: Canon Kabushiki KaishaInventor: Akio Goto
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Patent number: 8790523Abstract: A method for manufacturing a magnetic head, includes forming, on a non-magnetic film, a main magnetic pole film with a body portion and a write magnetic pole portion continuous with the body portion, and etching the non-magnetic film such that an undercut is formed around the body portion and beneath the write magnetic pole portion. The undercut penetrates beneath the write magnetic pole portion in a track width direction. The method includes wet etching the non-magnetic film beneath the main magnetic pole film at the undercut, the undercut being at least partially filled with an organic filler. The method also includes, after removal of the organic filler, covering at least both sides of the write magnetic pole portion with a magnetic gap film, and forming a write shield film adjacent to the magnetic gap film. The undercut forms a hollow in the non-magnetic film underlying the write magnetic pole portion.Type: GrantFiled: January 7, 2009Date of Patent: July 29, 2014Assignee: TDK CorporationInventors: Hisayoshi Watanabe, Yusuke Ide
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Patent number: 8784671Abstract: A method of manufacturing a press plate for applying a surface structure onto a floor panel, wherein the press plate includes a press plate surface, comprises the following steps: first fine projections are created on the press plate surface, then the resulting fine projections are covered by a surface treatment resistant material, and subsequently the press plate surface including the resistant material is submitted to a surface treatment.Type: GrantFiled: October 2, 2008Date of Patent: July 22, 2014Assignee: Spanolux N.V.-Div. BalterioInventor: Bruno Vermeulen
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Patent number: 8748323Abstract: A patterning method is provided. First, a substrate having an objective material layer thereon is provided. Thereafter, a mask layer is formed on the objective material layer. Afterwards, a patterned layer is formed over the mask layer, wherein a material of the patterned layer includes a metal-containing substance. Then, the mask layer is patterned to form a patterned mask layer. Further, the objective material layer is patterned, using the patterned mask layer as a mask.Type: GrantFiled: July 7, 2008Date of Patent: June 10, 2014Assignee: MACRONIX International Co., Ltd.Inventors: Han-Hui Hsu, Shih-Ping Hong, An-Chi Wei, Ming-Tsung Wu
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Patent number: 8722544Abstract: A method of simultaneously cleaning inorganic and organic contaminants from semiconductor wafers and micro-etching the semiconductor wafers. After the semiconductor wafers are cut or sliced from ingots, they are contaminated with cutting fluid as well as metal and metal oxides from the saws used in the cutting process. Aqueous alkaline cleaning and micro-etching solutions containing alkaline compounds and mid-range alkoxylates are used to simultaneously clean and micro-etch the semiconductor wafers.Type: GrantFiled: October 14, 2010Date of Patent: May 13, 2014Assignee: Rohm and Haas Electronic Materials LLCInventors: Robert K. Barr, Raymond Chan
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Patent number: 8685270Abstract: A method for producing a semiconductor wafer sliced from a single crystal includes rounding an edge using a grinding disk containing abrasives with an average grain size of 20.0-60.0 ?m. A first simultaneous double-side material-removing process is performed wherein the semiconductor wafers are processed between two rotating ring-shaped working disks, each working disk having a working layer containing abrasives having an average grain size of 5.0-20.0 ?m, wherein the semiconductor wafer is placed in a cutout in one of a plurality of carriers rotatable by a rolling apparatus such that the semiconductor wafer lies in a freely movable manner in the carrier and the wafer is movable on a cycloidal trajectory. A second simultaneous double-side material-removing process is performed including processing the semiconductor wafers between two rotating ring-shaped working disks, each working disk having a working layer containing abrasives having an average grain size of 0.5-15.0 ?m.Type: GrantFiled: October 12, 2010Date of Patent: April 1, 2014Assignee: Siltronic AGInventors: Juergen Schwandner, Thomas Buschhardt, Diego Feijoo, Michael Kerstan, Georg Pietsch, Guenter Schwab
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Patent number: 8673161Abstract: Methods for fabricating a device component are provided. A substrate comprising a RIE stop layer, an oxide layer formed on the RIE stop layer, and a RIE-able layer formed on the oxide layer may be provided. A resist layer may be patterned on the RIE-able layer. A metal layer may be formed on portions of the RIE-able layer that are not covered by the resist layer. The resist layer may be removed and an RIE performed to remove exposed portions of the RIE-able layer and portions of the oxide layer beneath the exposed portions of the RIE-able layer. Thereafter, the metal layer may be removed, and the component may be formed in an opening in the oxide layer formed during the RIE.Type: GrantFiled: December 29, 2008Date of Patent: March 18, 2014Assignee: HGST Netherlands B.V.Inventors: Christian R. Bonhôte, Jeffrey S. Lille, Ricardo Ruiz