Patents Examined by Thomas Pham
  • Patent number: 9358370
    Abstract: Embodiments hereof relate to a guidewire formed from an elongated shaft, at least a portion of the shaft having an outer layer, a plurality of channels formed through the outer layer, and an inner core. The outer layer is formed from a material non susceptible to erosion by an erosion agent and the inner core is formed from a radiopaque material susceptible to erosion by the erosion agent. When exposed to the erosion agent, core material adjacent to the channels is removed to form a pattern of integral radiopaque segments or markers with a plurality of voids therebetween. By controlling the location of channels and the rate of erosion of the core material, the pattern of integral radiopaque segments and voids allow for in situ measurement when viewed under fluoroscopy.
    Type: Grant
    Filed: March 12, 2012
    Date of Patent: June 7, 2016
    Assignee: Medtronic Vascular, Inc.
    Inventors: Mark L. Stiger, Richard L. Thomas
  • Patent number: 9340761
    Abstract: A substrate processing method includes an SPM supplying step of supplying SPM having high temperature to an upper surface of a substrate, a DIW supplying step of supplying, after the SPM supplying step, DIW having room temperature to the upper surface of the substrate to rinse off a liquid remaining on the substrate, and a hydrogen peroxide water supplying step of supplying, after the SPM supplying step and before the DIW supplying step, hydrogen peroxide water of a liquid temperature lower than the temperature of the SPM and not less than room temperature, to the upper surface of the substrate in a state where the SPM remains on the substrate.
    Type: Grant
    Filed: September 2, 2014
    Date of Patent: May 17, 2016
    Assignee: SCREEN Holdings Co., Ltd.
    Inventors: Sei Negoro, Ryo Muramoto, Yasuhiko Nagai, Tsutomu Osuka, Keiji Iwata
  • Patent number: 9341759
    Abstract: A method for manufacturing a polarizer may include forming a first barrier and a second barrier on a surface of a metal layer. The method may further include providing a copolymer layer between the first barrier and the second barrier. The method may further include processing the copolymer layer to form a processed polymer layer that includes first-polymer portions and second-polymer portions that are alternately disposed. The method may further include removing the second-polymer portions from the processed polymer layer to form polymer members that are spaced from each other. The method may further include etching the metal layer, using at least the polymer members, the first barrier, and the second barrier as a mask, to form a plurality of first-type wires and a plurality of second-type wires.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: May 17, 2016
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: TaeWoo Kim, Lei Xie, Minhyuck Kang, Myung Im Kim, Seung-won Park, Moongyu Lee, Sumi Lee
  • Patent number: 9336809
    Abstract: A method to fabricate an imprint template for bit-patterned magnetic recording media using block copolymers (BCPs) integrates data region patterning and servo region patterning. A heat sink layer is formed on the imprint substrate only in the data regions. A sublayer for the BCP is deposited over both the data regions and the servo regions and patterned to form stripes in the data regions and servo features in the servo regions. A BCP is then deposited in both the data and servo regions. Only the BCP in the data regions is heated, which causes phase separation of the BCP in the data regions into the two BCP components. The selective heating may be accomplished by directed controlled laser radiation to only the data regions. The heat sink layer below the data regions absorbs the heat from the laser radiation, confining it to the data regions.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: May 10, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Hitesh Arora, Sripathi Vangipuram Canchi, Franck Dreyfus Rose, Ricardo Ruiz, Vipin Ayanoor-Vitikkate
  • Patent number: 9338871
    Abstract: Methods and systems for controlling temperatures in plasma processing chamber with reduced controller response times and increased stability. Temperature control is based at least in part on a feedforward control signal derived from a plasma power input into the processing chamber. A feedforward control signal compensating disturbances in the temperature attributable to the plasma power may be combined with a feedback control signal counteracting error between a measured and desired temperature.
    Type: Grant
    Filed: October 15, 2010
    Date of Patent: May 10, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chetan Mahadeswaraswamy, Walter R. Merry, Sergio Fukuda Shoji, Chunlei Zhang, Yashaswini B. Pattar, Duy D. Nguyen, Tina Tsong, Shane C. Nevil, Douglas A. Buchberger, Jr., Fernando M. Silveira, Brad L. Mays, Kartik Ramaswamy, Hamid Noorbakhsh
  • Patent number: 9334570
    Abstract: A fixture for etching PCD drill inserts is provided. The fixture design allows the fixture to be injection molded, significantly reducing costs and allowing the fixture to be disposed of after a single use. The fixture allows for faster use and more accurate etching of the PCD insert.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: May 10, 2016
    Assignee: STINGRAY GROUP LLC
    Inventor: Allen Turner
  • Patent number: 9334197
    Abstract: A method for producing a ceramic composite for light conversion including first step of forming the step level difference such that an oxide crystal phase other than Al2O3 phase of a surface of a solidified body is in a convex shape relative to an Al2O3 phase by subjecting the surface of the solidified body having a structure in which the Al2O3 phase and the oxide crystal phase other than Al2O3 phase are continuously and three-dimensionally entangled with each other to dry etching, and a second step of reducing the step level difference by subjecting the solidified body subjected to the dry etching to CMP or MP.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: May 10, 2016
    Assignee: Ube Industries, Ltd.
    Inventors: Dai Inamori, Takafumi Kawano
  • Patent number: 9330926
    Abstract: A method of etching features into a silicon layer with a steady-state gas flow is provided. An etch gas comprising an oxygen containing gas and a fluorine containing gas is provided. A plasma is provided from the etch gas. Then, the flow of the etch gas is stopped.
    Type: Grant
    Filed: December 18, 2008
    Date of Patent: May 3, 2016
    Assignee: Lam Research Corporation
    Inventors: Robert Chebi, Frank Lin, Jaroslaw W. Winniczek, Wan-Lin Chen, Erin McDonnell, Lily Zheng, Stephan Lassig, Jeff Bogart, Camelia Rusu
  • Patent number: 9330990
    Abstract: Disclosed is a method for determining an endpoint of an etch process using optical emission spectroscopy (OES) data as an input. Optical emission spectroscopy (OES) data are acquired by a spectrometer attached to a plasma etch processing tool. The acquired time-evolving spectral data are first filtered and demeaned, and thereafter transformed into transformed spectral data, or trends, using multivariate analysis such as principal components analysis, in which previously calculated principal component weights are used to accomplish the transform. A functional form incorporating multiple trends may be used to more precisely determine the endpoint of an etch process. A method for calculating principal component weights prior to actual etching, based on OES data collected from previous etch processing, is disclosed, which method facilitates rapid calculation of trends and functional forms involving multiple trends, for efficient and accurate in-line determination of etch process endpoint.
    Type: Grant
    Filed: October 17, 2013
    Date of Patent: May 3, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Yan Chen, Serguei Komarov, Vi Vuong
  • Patent number: 9330928
    Abstract: A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum layer on a TiN layer on an HfO2 or ZrO2 layer on a substrate. In some embodiments, the method comprises a physical sputter process to selectively etch the platinum layer, followed by a plasma etch process comprises CHF3 and oxygen to selectively etch the TiN, HfO2 or ZrO2 layers with respect to the substrate.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: May 3, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Jinhong Tong, Frederick Carlos Fulgenico, ShouQian Shao
  • Patent number: 9330885
    Abstract: The embodiments disclose a method of stack patterning, including loading a stack into a stationary stack stage, rotating one or more ion beam grid assemblies substantially concentrically aligned with the stationary stack stage to etch the stack and controlling the operation of the one or more ion beam grid assemblies to achieve substantial axial uniformity of the etched stack.
    Type: Grant
    Filed: June 30, 2011
    Date of Patent: May 3, 2016
    Assignee: Seagate Technology LLC
    Inventors: Michael R. Feldbaum, Justin Jia-Jen Hwu, David S. Kuo, Gennady Gauzner, Li-Ping Wang
  • Patent number: 9330937
    Abstract: Two-step process sequences uniformly etch both tungsten-based and titanium-based structures on a substrate. A sequence of wet etches using peroxide and heated nitric acid uniformly recesses a metal stack that includes W, TiN, and TiAl. W, TiN and TiC are uniformly recessed by a peroxide etch at ˜25 C followed by an acid solution with a very small amount of added peroxide at ˜60 C. TiC is etched without etching trench oxides or other metals in a work-function metal stack by either (1) highly-dilute of ultra-dilute HF at 25-35 C, (2) dilute HCl at 25-60 C, (3) dilute NH4OH at 25-60 C, or (4) solution (2) or (3) with small amounts of peroxide. Other metals in the stack may then be plasma-etched without being blocked by TiC residues.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: May 3, 2016
    Assignee: Intermolecular, Inc.
    Inventors: Gregory Nowling, John Foster
  • Patent number: 9233840
    Abstract: A method for processing a structure. The structure is formed and includes a substrate, a substructure having a sidewall and disposed on the substrate, a first polymer structure disposed on the substrate, and a second polymer structure disposed on the substrate such that the first polymer structure is disposed between the sidewall and the second polymer structure. An aspect ratio of the first polymer structure, the second polymer structure, or both is reduced in a reducing step. One polymer structure (i.e., the first polymer structure or the second polymer structure) is selectively removed from the structure such that a remaining polymer structure (i.e., the second polymer structure or the first polymer structure) remains disposed on the external surface of the substrate after the one polymer structure has been selectively removed, wherein the aspect ratio of the remaining polymer structure was reduced in the reducing step.
    Type: Grant
    Filed: October 28, 2010
    Date of Patent: January 12, 2016
    Assignees: International Business Machines Corporation, JSR Corporation
    Inventors: Joy Cheng, Hayato Namai, Daniel P. Sanders
  • Patent number: 9196501
    Abstract: According to one embodiment, a method for chemical planarization includes: preparing a treatment liquid containing a hydrosilicofluoric acid aqueous solution containing silicon dioxide dissolved therein at a saturated concentration; and decreasing height of irregularity of a silicon dioxide film. In the decreasing, dissolution rate of convex portions is made larger than dissolution rate of concave portion of the irregularity while changing equilibrium state of the treatment liquid at areas being in contact with the convex portions of the irregularity, in a state in which the silicon dioxide film having the irregularity is brought into contact with the treatment liquid.
    Type: Grant
    Filed: March 16, 2012
    Date of Patent: November 24, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masako Kodera, Yukiteru Matsui
  • Patent number: 9165770
    Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: October 20, 2015
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Ming He, Seowoo Nam, Craig Child
  • Patent number: 9159551
    Abstract: A method of forming a capacitor includes depositing a dielectric metal oxide layer of a first phase to a thickness no greater than 75 Angstroms over an inner conductive capacitor electrode material. The first phase dielectric metal oxide layer has a k of at least 15. Conductive RuO2 is deposited over and into physical contact with the dielectric metal oxide layer. Then, the RuO2 and the dielectric metal oxide layer are annealed at a temperature below 500° C. The RuO2 in physical contact with the dielectric metal oxide during the annealing facilitates a change of the dielectric metal oxide layer from the first phase to a second crystalline phase having a higher k than the first phase. The annealed dielectric metal oxide layer is incorporated into a capacitor dielectric region of a capacitor construction. Other implementations are disclosed.
    Type: Grant
    Filed: July 2, 2009
    Date of Patent: October 13, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Vassil Antonov, Vishwanath Bhat
  • Patent number: 9147423
    Abstract: A method for making a bit-patterned-media magnetic recording disk with discrete magnetic islands includes annealing the data islands after they have been formed by an etching process. A hard mask, such as a layer of silicon nitride or carbon, may be first formed on the recording layer and a patterned resist formed on the hard mask. The resist pattern is then transferred into the hard mask, which is used as the etch mask to etch the recording layer and form the discrete data islands. After the data islands are formed by the etching process, the patterned recording layer is annealed. The annealing may be done in a vacuum, or in an inert gas, like helium or argon, or in a forming gas such as a reducing atmosphere of argon plus hydrogen. The annealing improves the coercivity, the effective saturation magnetization and the thermal stability of the patterned media.
    Type: Grant
    Filed: April 17, 2012
    Date of Patent: September 29, 2015
    Assignee: HGST Netherlands B.V.
    Inventors: Michael Konrad Grobis, Olav Hellwig, Ernesto E. Marinero, Andrew Thomas McCallum, Dieter K. Weller
  • Patent number: 9115022
    Abstract: A high resolution stencil is produced by a thermal printer for the purposes of permanently etching glass for parts identification, tracking and labeling. An improved process to attach the stencil to the glass substrate is defined. An amended aqueous adhesive is used to bind the stencil so that it is in direct contact with the glass at all times and across the entire plane of the stencil and the adhesion is aided by use of a straight-edged tool to help evacuate any potential elements which may hinder the prescribed glass etching compound(s) from completing a clear and precise permanent mark.
    Type: Grant
    Filed: February 21, 2013
    Date of Patent: August 25, 2015
    Inventor: Matthew R. Holloway
  • Patent number: 9082719
    Abstract: Embodiments provide a method for removing a dielectric layer from a bottom of a trench while maintaining the dielectric layer on sidewalls of the trench. The method includes etching the dielectric layer at the bottom of the trench and generating a passivation layer on the dielectric layer at an upper portion of the trench by adjusting the conditions of a plasma etch process to a first mode; and a step of etching the dielectric layer at the bottom of the trench and etching the passivation layer at the upper portion of the trench by adjusting the conditions of the plasma etch process to a second mode before the dielectric layer at the bottom of the trench is completely removed.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: July 14, 2015
    Assignee: Infineon Technologies AG
    Inventors: Lothar Brencher, Carsten Moritz
  • Patent number: 9074118
    Abstract: An aqueous chemical-mechanical polishing composition for polishing metal containing substrates comprising an abrasive particle consisting essentially of a primary particle modified with an aluminosilicate layer, and wherein the abrasive particle has a zeta potential measured at pH 2.3 of about ?5 mV to about ?100 mV. The composition can be used to polish the surface of a tungsten containing substrate.
    Type: Grant
    Filed: July 6, 2007
    Date of Patent: July 7, 2015
    Assignee: Cabot Microelectronics Corporation
    Inventors: Robert Vacassy, Renjie Zhou