Abstract: A method of displaying a schematic diagram of an integrated circuit design is disclosed. The integrated circuit design includes a plurality of logic blocks and the schematic diagram may include a plurality of connections between respective pairs or groups of the logic blocks. The method includes identifying a plurality of interconnect lines that is adapted to schematically illustrate the plurality of connections. Selected interconnect lines out of the plurality of interconnect lines is identified. Portions of the selected interconnect lines may be channeled through a global connection line on the schematic diagram. The global connection line may be a graphical line that spans from one edge of the schematic diagram to another.

Abstract: A semiconductor die is described. This semiconductor die includes a driver, and a spatial alignment transducer that is electrically coupled to the driver and which is proximate to a surface of the semiconductor die. The driver establishes a spatially varying electric charge distribution in at least one direction in the spatial alignment transducer, thereby facilitating determination of a spatial alignment in more than one direction between the semiconductor die and another semiconductor die. In particular, a spatial alignment sensor proximate to the surface of the other semiconductor die may detect an electrical field (or an associated electrostatic potential) associated with the spatially varying electric charge distribution. This detected electric field may allow the vertical spacing between the surfaces of the semiconductor dies and/or an angular alignment of the semiconductor dies to be determined.

Abstract: Various embodiments identify a design including circuit features and identify an operation that produces an aggressor for victim(s). The operation on the aggressor and the set of victims are implemented using local maximally spanning spacetile(s) while satisfying some design requirements. Where the set of victims includes interconnects, the design may allow no bend in some interconnects. One or more spacetiles are used to perform the operation on the aggressor and implement the interconnects while introducing no bends in the interconnects by using local maximally spanning spacetile(s). Some implementation may perform block modeling for the aggressor to perform the operation on the aggressor and implement a set of victims while preserving the relative order of the interconnects by using the block modeling for the aggressor.

Abstract: A system and method for balancing the capacitive charge on touch sensor electrodes so that every two adjacent routes have the same capacitance as any other adjacent two routes, wherein routing electrodes are spaced further and further apart, or graduated, as they get longer, to thereby balance the capacitance on the touch sensor electrodes without having to add or subtract an offset from each touch sensor electrode.

Abstract: The present disclosure relates to a method for routing in an electronic circuit design. The method may include assigning a plurality of rats interconnecting one or more terminals associated with a layout of the electronic circuit design to a bundle. The method may also include generating an independent breakout of the plurality of rats from a source end and a target end of the bundle. The method may further include sequencing the plurality of rats within the assigned bundle to generate a defined sequence of rats within the assigned bundle based upon, at least in part, the source end of the bundle. The method may additionally include generating a costed sequence breakout at the target end of the bundle, based upon, at least in part, a costed sequence analysis. The method may also include determining if the costed sequence breakout meets at least one criteria associated with the electronic design.

Abstract: Systems and techniques for creating a netlist abstraction are described. During operation, an embodiment can receive a netlist for a circuit design, wherein circuit elements in the circuit design are organized in a logical hierarchy (LH). Next, the embodiment can receive a set of LH nodes in the LH. The embodiment can then create the netlist abstraction by, for each LH node in the set of LH nodes, replacing a portion of the netlist that is below the LH node by a star netlist, wherein the star netlist includes a center object that is electrically connected to a set of satellite objects, wherein each satellite object corresponds to a port of the LH node.

Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.

Abstract: Various embodiments identify a design including circuit features and identify an operation that produces an aggressor for victim(s). The operation on the aggressor and the set of victims are implemented using local maximally spanning spacetile(s) while satisfying some design requirements. Where the set of victims includes interconnects, the design may allow no bend in some interconnects. One or more spacetiles are used to perform the operation on the aggressor and implement the interconnects while introducing no bends in the interconnects by using local maximally spanning spacetile(s). Some implementation may perform block modeling for the aggressor to perform the operation on the aggressor and implement a set of victims while preserving the relative order of the interconnects by using the block modeling for the aggressor.

Abstract: The present disclosure relates to a method for visualizing an electronic circuit design. The method may include receiving the electronic circuit design, wherein the electronic circuit design includes at least one timing constraint. The method may also include identifying the at least one timing constraint and displaying, at a graphical user interface associated with the one or more computing devices, the at least one timing constraint and a physical routing associated with the electronic circuit design. The method may further include receiving a user input associated with the electronic circuit design and dynamically updating a graphical representation of the at least one timing constraint, in response to the received user input.

Abstract: In a semiconductor device design method performed by at least one processor, location data of at least one electrical component in a layout of a semiconductor device is extracted by the at least one processor. Voltage data associated with the at least one electrical component and based on a simulation of an operation of the semiconductor device is extracted by the at least one processor. Based on the extracted location data, the extracted voltage data is incorporated, by the at least one processor, in the layout to generate a modified layout of the semiconductor device.

Abstract: A method for laying out a target pattern includes assigning a keep-out zone to an end of a first feature within a target pattern, and positioning other features such that ends of the other features of the target pattern do not have an end within the keep-out zone. The target pattern is to be formed with a corresponding main feature and cut pattern.

Abstract: Embodiments that design integrated circuits using a 1×N compiler in a closed-loop 1×N methodology are disclosed. Some embodiments create a physical design representation based on a behavioral representation of a design for an integrated circuit. The behavioral representation may comprise RTL HDL with one or more 1×N building blocks. The embodiments may alter elements of the 1×N building block by using logic design tools, synthesis tools, physical design tools, and timing analysis tools. Further embodiments comprise an apparatus having a first generator to generate a behavioral representation of a design for an integrated circuit, a second generator to generate a logical representation of the design, and a third generator to generate a physical design representation of the design, wherein the representation generators may create updated versions of the representations which reflect alterations made to 1×N building block elements.

Abstract: An embodiment of a method of high-level synthesis of a dataflow pipeline is disclosed. This embodiment includes obtaining processes from the high-level synthesis of the dataflow pipeline. A schedule for read operations and write operations for first-in, first-out data channels of the processes is determined. A dataflow through the dataflow pipeline for the schedule is determined. An edge-weighted directed acyclic graph for the processes and the dataflow is generated. A longest path in the edge-weighted directed acyclic graph is located. A weight for the longest path is output as an estimate, such as a latency estimate for example, for the dataflow.

Abstract: Methods and apparatuses for circuit design to reduce power usage, such as reducing temperature dependent power usage, and/or to improve timing, such as reducing temperature dependent delay or transition time. At least one embodiment of the method implemented on a data processing system for circuit design, the method comprises determining for a first design of a circuit a first temperature solution and a first power dissipation solution, the first power dissipation solution and the first temperature solution being interdependent, and transforming the first design of the circuit into a second design of the circuit using the first temperature solution to reduce leakage power of the circuit under one or more design constraints.

Abstract: A delay parameter extracting apparatus includes a schematic composing unit, a layout composing unit, a verification unit, and a parameter extracting unit. The schematic composing unit is configured to: facilitate design of a schematic circuit; and generate a first net list based on the design of the schematic circuit. The layout composing unit is configured to: facilitate design of a layout based on the schematic circuit; and generate a second net list based on the design of the layout. The verification unit is configured to verify the layout by comparing the first net list to the second net list. The parameter extracting unit is configured to: extract capacitance (C) values from the layout; and extract delay parameters based on the C values with respect to respective nets according to types of delay parameters associated with the respective nets.

Abstract: An integrated circuit chip is disclosed having a semiconductor substrate and a plurality of conduction layers (metalz, metalz+1), disposed on the semiconductor substrate and separated by dielectric layers, for distribution of power and electrical signals on the chip. The integrated circuit chip comprises a power-supply distribution network (200) which comprises, in a first one (metalz) of the conduction layers, a first mesh structure (210) of electrically conductive material for distribution of a first electrical potential (POWER) of the power supply. The power-supply distribution network also comprises, in a second one (metalz+1) of the conduction layers, different from the first one of the conduction layers, a second mesh structure (220) of electrically conductive material for distribution of a second electrical potential (GROUND) of the power supply.

Abstract: A method of for compensating for variations in structures of an integrated circuit. The method includes (a) selecting a mask design shape and selecting a region of the mask design shape; (b) applying a model-based optical proximity correction to all of the mask design shape; and after (b), (c) applying a rules-based optical proximity correction to the selected region of the mask design shape.

Abstract: An adaptive template system for an automated PCB manufacturing release package system includes a PCB database including PCB CAD data associated with a CAD file of PCB design. A shape engine is configured to read the PCB CAD data and display simultaneous views of a given PCB from the PCB database including different views of the PCB and configured to create reconfigurable objects displayed simultaneously in the form of different views of the PCB such that any change in the design of the PCB is reflected in the different views. One or more selectable adaptive templates, and an adaptive template object in the shape engine are configured to: read a selected adaptive template, generate a view of the adaptive template which provides for input of user-entered data, and retain the user-entered data in the adaptive template.

Abstract: A programmable device system includes one or more network-on-chip (NoC) die layers vertically connected to one or more programmable chip dice layers. The NoC die layer includes interconnects, a bus or non-blocking switches, and optionally memory blocks and direct memory access engines. The NoC die layer improves on-chip communications by providing fast and direct interconnection circuitry between various parts of the programmable chip die.

Abstract: A circuit verification method for a logic circuit is presented. The method includes developing a first hardware description language (HDL) code representative of the logic circuit and, for an embedded portion of the logic circuit, developing a second HDL code representative of the embedded portion. The second HDL code includes a process of forcing inputs of the embedded portion to one or more known values. The method further includes operating a processing device in conjunction with the first and second HDL codes and verifying operation of the embedded portion in response to forcing the inputs to the logic circuit.