Abstract: The present disclosure describes a method of optimizing a design for manufacture (DFM) simulation. The method includes receiving an integrated circuit (IC) design data having a feature, receiving a process data having a parameter or a plurality of parameters, performing the DFM simulation, and optimizing the DFM simulation. The performing the DFM simulation includes generating a simulation output data using the IC design data and the process data. The optimizing the DFM simulation includes generating a performance index of the parameter or the plurality of parameters by the DFM simulation. The optimizing the DFM simulation includes adjusting the parameter or the plurality of parameters at outer loop, middle loop, and the inner loop. The optimizing the DFM simulation also includes locating a nadir of the performance index of the parameter or the plurality of parameters over a range of the parameter or the plurality of parameters.

Abstract: A method for expressing a hierarchy of scalabilities in complex systems, including a discrete event simulation and an analytic model, for analysis and prediction of the performance of multi-chip, multi-core, multi-threaded computer processors is provided. Further provided is a capacity planning tool for migrating data center systems from a source configuration which may include source systems with multithreaded, multicore, multichip central processing units to a destination configuration which may include destination systems with multithreaded, multicore and multichip central processing units, wherein the destination systems may be different than the source systems. Apparatus and methods are taught for the assembling of and utilization of linear and exponential scalability factors in the capacity planning tool when a plurality of active processor threads populate processors with multiple chips, multiple cores per chip and multiple threads per core.

Abstract: A circuit design support method that is executed by a computer, includes calculating a first performance value of a circuit under design before a layout process, by inputting into a first function model that represents a performance value of the circuit under design before the layout process, the values of parameters among parameters of a second parameter group and corresponding to parameters of a first parameter group; acquiring a second performance value that is of the circuit under design after the layout process and obtained by simulating operation of the circuit under design after the layout process, using the values of the parameters of the second parameter group; and generating based on the calculated first performance value, the acquired second performance value, and the second parameter group, a second function model that represents a difference in the performance value of the circuit under design before and after the layout process.

Abstract: A method for correcting layout pattern and a mask having the corrected layout pattern thereon are provided. In an exemplary method, a first layout pattern including a plurality of first hole patterns can be provided to form an auxiliary pattern in each first hole pattern and to obtain a second layout pattern. The auxiliary pattern can have a dimension smaller than an exposure resolution in a photolithography process. The second layout pattern can then be processed by an optical proximity correction (OPC) to obtain a first modified layout pattern. The first modified layout pattern can include a plurality of modified first hole patterns modified by the OPC. The first modified layout pattern can be simulated to obtain an actual layout pattern such that the actual layout pattern and the first layout pattern have an edge placement error (EPE) within a predetermined range.

Abstract: Embodiments of a system and method for generating an image configured to program a parallel machine from source code are disclosed. One such parallel machine includes a plurality of state machine elements (SMEs) grouped into pairs, such that SMEs in a pair have a common output. One such method includes converting source code into an automaton comprising a plurality of interconnected states, and converting the automaton into a netlist comprising instances corresponding to states in the automaton, wherein converting includes pairing states corresponding to pairs of SMEs based on the fact that SMEs in a pair have a common output. The netlist can be converted into the image and published.

Abstract: Described are a system and method to control interface timing and/or voltage operations of signals transmitted between devices. A processor may be coupled through one or more bus interfaces of a bus to one or more corresponding interface timing and/or voltage comparison circuits and corresponding interface timing and/or voltage adjustment circuits.

Abstract: A library of cells for designing an integrated circuit, the library comprises continuous diffusion compatible (CDC) cells. A CDC cell includes a p-doped diffusion region electrically connected to a supply rail and continuous from the left edge to the right edge of the CDC cell; a first polysilicon gate disposed above the p-doped diffusion region and electrically connected to the p-doped diffusion region; an n-doped diffusion region electrically connected to a ground rail and continuous from the left edge to the right edge; a second polysilicon gate disposed above the n-doped diffusion region and electrically connected to the n-doped diffusion region; a left floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the left edge; and a right floating polysilicon gate disposed over the p-doped and n-doped diffusion regions and proximal to the right edge.

Abstract: Provided is a system and method for assessing a design layout for a semiconductor device level and for determining and designating different features of the design layout to be formed by different photomasks by decomposing the design layout. The features are designated by markings that associate the various device features with the multiple photomasks upon which they will be formed and then produced on a semiconductor device level using double patterning lithography, DPL, techniques. The markings are done at the device level and are included on the electronic file provided by the design house to the photomask foundry. In addition to overlay and critical dimension considerations for the design layout being decomposed, various other device criteria, design criteria processing criteria and their interrelation are taken into account, as well as device environment and the other device layers, when determining and marking the various device features.

Abstract: In a semiconductor device design method performed by at least one processor, at least one first parasitic parameter between electrical components inside a region of a layout of a semiconductor device and at least one second parasitic parameter between electrical components outside the region of the layout are extracted by different tools. The extracted parasitic parameters are incorporated into the layout.

Abstract: A method of generating a circuit layout of an integrated circuit includes generating layout geometry parameters for at least a predetermined portion of an original netlist of the integrated circuit. A consolidated netlist including information from the original netlist and the layout geometry parameters is generated. Then, the circuit layout is generated based on the consolidated netlist.

Abstract: Disclosed are methods, systems, and articles of manufacture for using pattern matching with an integrated circuit layout including recognizing shapes within the IC layout, identifying features for the shapes, and extracting situations for the respective features. The method may further include simulating the situations to determine a set of situations for modification based on an OPC requirement, modifying the set of situations to improve satisfaction of the OPC requirement, and reintegrating the modified set of situations into the IC layout. The method may also include simulating a subset of the extracted situations to determine aerial images of the subset, and tiling the subset of situations to form a larger aerial image. The method may also include removing overlap from a window based on the situations extracted for the window, calculating a density for each of the situations, and calculating a density for the window based on the density.

Abstract: A method for process proximity correction may include obtaining a point spread function (PSF) from test patterns, the test patterns including an etching process performed thereon, generating a target layout with polygonal patterns, dividing the target layout into grid cells, generating a density map including long-range layout densities, each of the long-range layout densities being obtained from the polygonal patterns located within a corresponding one of the grid cells, performing a convolution of the long-range layout densities with the PSF to obtain long-range etch skews for the grid cells, and generating an etch bias model including short-range etch skews and the long-range etch skews, each of the short-range etch skews being obtained from a neighboring region of a target pattern selected from the polygonal patterns in each of the grid cells.

Abstract: Automatically modifying a layout to perform circuit simulation. Initially, a first layout of the electronic system may be received or stored. A second layout of the electronic system may be automatically generated based on the first layout. The automatic generation may involve automatically simplifying the first layout using a set of rules for electromagnetic (EM) simulation. The second layout may then be used to perform EM simulation of the electronic system, e.g., to perform verification.

Abstract: Some embodiments provide a system that facilitates the creation of a layout from a schematic in an electronic design automation (EDA) application. During operation, the system performs a tiered comparison of the schematic and the layout. The tiered comparison includes a first tier that compares labels in the schematic and the layout. The tiered comparison also includes a second tier that compares first-level connectivity in the schematic and the layout. The tiered comparison further includes a third tier that determines a graph isomorphism between the schematic and the layout. After the tiered comparison is completed, the system provides a result of the tiered comparison to a user of the EDA application. Finally, the system enables repairs of mismatches in the result by the user through a graphical user interface (GUI) associated with the EDA application.

Abstract: A method for designing a dummy pattern that is formed in a vacant section of a chip region before a semiconductor substrate including the chip region that has a device graphics data section in which a circuit element pattern is formed and the vacant section in which the circuit element pattern is not formed is planarized by a chemical mechanical polishing process, the method includes: setting an overall dummy section on the entire chip region; setting a mesh section on the entire overall dummy section; dividing the overall dummy section by the mesh section so that a plurality of rectangular dummy patterns is formed on the entire chip region after the mesh section is set; and removing or transforming a part of the rectangular dummy patterns, thereby uniformizing a density of the dummy pattern in the chip region.

Abstract: A computer program for generating a layout for a ferroelectric random access memory (FRAM) that is embodied on a non-transitory storage medium and executable by a processor is provided. FRAM specifications are received, and an FRAM floorplan and design rules are retrieved from the non-transitory storage medium. The layout for the FRAM based on the FRAM specifications and design rules is then assembled.

Abstract: The Hessian (second derivative) of the image log slope (ILS) can be quickly and accurately calculated without the need to use approximate methods from the gradient of the ILS with respect to mask transmission and source intensity. The Hessian has been traditionally calculated using a finite-difference approach. Calculating the Hessian through a finite-difference approach is slow and is an approximate method. The gradient of the ILS improves the speed of calculation of the Hessian, and thus accelerated SMO operation is realized. The results of ILS evaluation can be used in design for manufacturing (DFM) to suggest changes in the design rules to improve imaging. For a fixed illumination, this information can help remove forbidden pitches and help select design rules for 1-D and 2-D patterns on a mask design layout.

Abstract: The disclosure relates to the analysis of compensated layout shapes. A method in accordance with an embodiment includes: analyzing a semiconductor layout using a bucket structure, the layout including a semiconductor device; and applying a pattern template to a content of the bucket structure to identify a shape adjacent to the semiconductor device; wherein the pattern template is derived from layout groundrules.

Abstract: One embodiment of the present invention provides a system that attempts to satisfy routing rules during routing of an integrated circuit (IC) chip design. During operation, the system receives a routing solution for the IC chip design and a set of routing rules to be satisfied by the routing solution. The system then assigns weights to the set of routing rules, wherein a higher weight for a routing rule indicates a higher importance of the routing rule. The system additionally assigns effort levels to the set of routing rules, wherein a higher effort level for a routing rule indicates that a higher amount of resources are available to satisfy the routing rule. The system then modifies the routing solution to satisfy the routing rules based at least on the weights and the effort levels associated with the routing rules.

Abstract: A logic verification program, method and system that segments simulation results and then processes the resulting segments separately, and optionally in parallel, reduces memory and other system requirements and improves efficiency of verification of digital logic designs. The verification process fixes up event dependency check for past-directed checkers by including additional information with each segment after an initial segment that describes at least a portion of a state of the logic design, so that resultant events in the current segment that are caused by events in the previous segment(s) can be traced back to those events. Future directed checks are fixed-up by either repeating a failed check with a concatenation of the current segment and a next segment, or by providing an overlap between segments to ensure that the expected time duration between a causative event and the resulting event are included within the same segment file.