Abstract: Method for generating a reduced snapshot image for booting and a computing apparatus are provided. An embodiment of the method includes the following. In response to a shutdown request, it is determined whether a specific boot mode is enabled. When the specific boot mode is enabled, a threshold parameter set for process killing is assigned. If a first memory unit of the computing apparatus has at least one process satisfying a process killing condition, the at least one process satisfying the process killing condition is killed. The process killing condition includes a criterion based on the threshold parameter set. A hibernation process is entered, wherein the hibernation process generates a snapshot image for booting and stores the snapshot image in a second memory unit of the computing apparatus and the snapshot image includes at least one process reserved in the first memory after the killing step.

Abstract: A single-wire bootloader software architecture is disclosed that interfaces with any host device that has a serial port to program memory of a target device using only a single general-purpose I/O pin. The single-wire bootloader does not require any chip hardware resource modules. Instead, the single-wire bootloader implements a single-wire UART in software that monitors a single general-purpose I/O pin for commands from the host device.

Abstract: Embodiments of the present invention disclose a method and device for selecting a sampling clock signal. The method includes: obtaining, by a logic chip, a data edge of a data signal and a clock edge of a clock signal, selecting a sampling edge according to the data edge and the clock edge, and sending a selecting signal corresponding to the sampling edge to a selector; and selecting, by the selector, a sampling clock signal according to the selecting signal. The technical solutions provided by the embodiments of the present invention can solve problems of poor system maintainability and high cost of operation and maintenance because a receiver device needs to select a sampling clock signal through manual configuration in the synchronous serial-port communication in the prior art.

Abstract: A system and method of dynamically managing a power supply allocation for each one of the server blades in a blade server includes a blade server system having a blade chassis, multiple server blades coupled to the blade chassis, a power supply system coupled to the blade chassis, a chassis management module coupled to the blade chassis, wherein the blade chassis includes electrical and data communication interconnections between the server blades, the redundant power supply system and the chassis management module. The chassis management module includes computer readable media having program instructions for dynamically managing a power supply allocation for each one of the server blades.

Abstract: In one embodiment, the present invention includes a method for generating a list of files accessed during an operating system (OS) boot process to profile the OS boot process, and optimizing the list of files to generate an optimized file list for use in future OS boot processes, where the optimizing is according to a first optimization technique if the files were accessed from a solid state medium and according to a second optimization technique if the files were accessed from a rotating medium. Other embodiments are described and claimed.

Abstract: A system and method for switching in an energy efficient network. Rapid switching between multiple operating modes can generate a voltage spike or voltage lag on an on-board inductor. Suppression of the voltage spike or voltage lag can be enabled through the activation of by a physical layer device of an inductor bypass path at a time proximate to the switching between multiple operating modes.

Abstract: An embodiment for skew compensation for a stacked die is disclosed. For an embodiment of an apparatus, an interposer has a first and a second integrated circuit die coupled to the interposer. The first integrated circuit die includes an information generator, a signal delay compensator, and an input/output block. The information generator is configured to determine: a first delay value for a first path of the interposer between the first integrated circuit die and the second integrated circuit die; a second delay value for a second path of the interposer between the first integrated circuit die and the second integrated circuit die; and a difference between the first delay value and the second delay value. The signal delay compensator is coupled to receive the difference and configured to adjust a parameter of the first integrated circuit die to reduce the difference.

Abstract: Techniques and apparatuses for providing power-aware thread scheduling and dynamic use of processors are disclosed. In some aspects, a multi-core system is monitored to determine core activity. The core activity may be compared to a power policy that balances a power savings plan with a performance plan. One or more of the cores may be parked in response to the comparison to reduce power consumption by the multi-core system. In additional aspects, the power-aware scheduling may be performed during a predetermined interval to dynamically park or unpark cores. Further aspects include adjusting the power state of unparked cores in response to the comparison of the core activity and power policy.

Abstract: An image processing apparatus being configured to support a power-saving mode which allows achieving low power consumption while keeping an idle connection without communication between the image processing apparatus and a communication device in a network environment, comprises: a first judgment portion which judges whether or not the communication device supports the power-saving mode; and a communicator which establishes a connection to the communication device at a first communication rate if the first judgment portion judges that the communication device does not support the power-saving mode, at a second communication rate which is faster than the first communication rate if the first judgment portion judges that the communication device supports the power-saving mode.

Abstract: The present disclosure is directed to a system including a power source connected to at least two electrical buses, and a battery connected to each one of the electrical buses. Each battery is charged by the power source and is connected to a load via one of the electrical buses. A battery error signal generator generates a battery error signal for each battery by finding a difference between a sensed battery voltage and a reference voltage. A reference control signal generator generates a reference control signal for each battery based on the battery error signals for each battery. A power sensor produces a sensed power signal between the power source and each battery connected to each of the two electrical buses. The reference control signal and the sensed power signal for each battery controls a power output value from the power source to each battery.

Abstract: An information processing apparatus includes a receiver configured to receive a packet via a communication line, an operating processor configured to suspend an operation thereof when the information processing apparatus is in an energy saving mode, a first storage configured to store the packet received by the receiver, a determining unit including a table in which different operations of the operating processor are recorded in association with different patterns of packets and configured to determine whether to restart the operating processor when the information processing apparatus is in the energy saving mode based on a pattern of the packet stored in the first storage and the patterns of the packets in association with the operations of the operating processor recorded in the table, and a power manager configured to supply power to the operating processor based on a result determined by the determining unit to restart the operating processor.

Abstract: A central processing unit (CPU) power controller includes a power supply unit, a CPU power controller, a detecting circuit, a temperature compensation circuit, an inductor, a thermistor, first and second switches, and first and second capacitors. The detecting circuit outputs a detected voltage of an inductor to the CPU power controller. The temperature compensation circuit outputs a detected voltage of the thermistor to the CPU power controller, to compensate for changes in the voltage of the inductor. If the detected voltage is greater than the rated voltage, the first switch is opened and the second switch is closed. The inductor discharges. If the detected voltage of the inductor is less than the rated voltage, the first switch is closed and the second switch is opened, the power supply unit charges the inductor to increase the voltage of the CPU.

Abstract: An OOB sequence monitoring unit detects that an OOB sequence carried out between a base device as a superior device and a connection I/F which operates even if an extension device is in a standby state has proceeded to a given stage. Based on the detection by the OOB sequence monitoring unit, a power supply control unit instructs a starting power supply unit to supply power. When the extension device starts, the OOB sequence is carried out between the extension device and the connection I/F of another extension device in the same manner. As a result, extension devices are started in decreasing order from the extension device closest to the superior device.

Abstract: A port power switch (PPS) may be used for lead compensation in systems where power is provided to a connected device by a switch-mode power supply (SMPS). The PPS may be designed to co-operate with the SMPS, providing a mechanism for the feedback reference point of the SMPS to be automatically switched, in the event of system fault or some other condition that might result in the PPS entering an “OFF’ operating mode, from the application point of load (POL) to the voltage input pin of the PPS without loss of power path continuity. The switching mechanism and the PPS may be manufactured to reside on the same integrated circuit. The PPS may include a control block that generates a control signal to couple the feedback port of the SMPS to the POL under normal operation, and to the voltage input port of the PPS during a fault condition.

Abstract: A method of performing and correcting a timing analysis performed by a data processing apparatus on a circuit formed of a plurality of cells to account for the reverse Miller effect. The timing analysis steps includes identifying cells on and in parallel with a signal path that are driven by a same signal and determining an output transition time and a delay using the characterization data for the cell. The correcting steps includes providing further characterization data for some of the cells; correcting the output transition time for some of the cells by increasing the output transition time by an amount dependent upon the Miller capacitance for the cell and using the correction to the output transition time to correct an input transition time for a next cell; and calculating a time taken for a data signal to travel along the signal path from the delay times.

Abstract: There is provided a method of scheduler assisted power management for semiconductor devices. By accessing and analyzing workload data for tasks to be completed, a scheduler may provide finer grained control for determining and implementing an efficient power management policy. In this manner, tasks with completion deadlines can be allocated sufficient resources without wasteful power consumption resulting from ramping up of performance through overestimating of voltage or frequency increases. Additionally, power management may be planned for longer periods, rather than looking only at immediate data to be processed and constantly fluctuating voltage and frequency. In this manner, power management can run more smoothly and efficiently compared to conventional means of power management that ignore data from a scheduler when determining power management policy.

Abstract: A method and apparatus for generating an accurate clock generator timing source, comprising minimal jitter, excellent resolution, and an extended calibration range, for use, for example, in a system requiring accurate low power operation. In particular, a clock generation system is adapted to receive a generated clock input, a reference clock input, and an adjustment parameter comprising a sign bit and p data bits. The calibration logic system is further adapted to output and modify a calibrated clock, using distributed pulse modification. The adjustment parameter may be automatically generated.

Abstract: Power management architectures, methods and systems for programmable integrated circuit are disclosed. One embodiment of the present invention pertains to a power management software architecture which comprises power management modules each associated with a respective driver. Each driver is associated with a component of a programmable integrated circuit and displayable as a graphic image within an on-screen display of an integrated circuit design tool for programming the programmable integrated circuit. In addition, each power management module is operable to report power consumption data customized to its respective driver. The power management software architecture also comprises a power source module associated with a power source for the programmable integrated circuit for reporting power supply characteristics.

Abstract: An SoC is connected to an SDRAM that is controlled by a memory controller and a memory PHY, and the SoC is operable in a normal mode and in a power saving mode. The SoC includes a block A to be powered off in the power saving mode and a block B not to be powered off in the power saving mode. A memory controller is included in the block A. A memory PHY and signal level holding cells are included in the block B. The signal level holding cells are provided between the memory controller and the memory PHY, and are configured to fix output signals from the memory controller at predetermined levels in the power saving mode.

Abstract: The present invention relates to platform power management.