Abstract: A system and method for managing processing resources in a communication device having a power unit with distributed processing capability. In one aspect, digital power control processors that are configured to perform power system tasks and signal processing tasks are reconfigured by reallocating the tasks among the processors in order to balance the processing loads.

Abstract: Techniques are disclosed for managing the amount of power consumed by server components of a computer system, each server component having multiple power modes. The utilization of each server component is monitored. Based on the monitored utilization, a time period is determined in which to apply a selected power mode to the respective server component. The respective server component is configured to operate in the selected power mode for at least the determined time period.

Abstract: A system including an integrated circuit (IC) and a power supply regulator external to the IC. The IC operates in accordance with an active mode and a lower power mode, and is configured to retain a logical state during the low power mode. The power supply regulator is configured to i) supply a first voltage potential to a first pin of the IC during the active mode, and ii) disable the first voltage potential during the low power mode. The IC is configured to provide a first feedback signal from an internal supply of the IC to the power supply regulator via the first pin.

Abstract: A dynamic clock frequency module includes a request evaluation module configured to generate a sum of requests to utilize a system bus from a plurality of modules. A frequency assignment module is configured to calculate a clock frequency for the system bus in response to the requests and adjust the clock frequency between at least two non-zero frequency values. A pulse stretch module is configured to increase a period of time that at least one of the requests is asserted in response to the sum.

Abstract: A method for processing power-off suitable for a server system is provided. The server system includes a first node, a second node, and a power supply. The first and second nodes share the power supply. The method includes the following steps. A power-off process is performed by the first and second nodes respectively according to a power-off signal. An interception process is activated to intercept a completion signal generated in the power-off process, and an interrupt is triggered. The interrupt is performed by an interrupt handler, so as to detect whether the first and second nodes complete a power-off process. When the first and second nodes already complete the power-off process, the interception process is inactivated and the generated completion signal is recovered and transferred to the power supply for turning off a power.

Abstract: Techniques are disclosed for managing the amount of power consumed by server components of a computer system, each server component having multiple power modes. The utilization of each server component is monitored. Based on the monitored utilization, a time period is determined in which to apply a selected power mode to the respective server component. The respective server component is configured to operate in the selected power mode for at least the determined time period.

Abstract: An integrated circuit comprising a plurality of functional blocks, each functional block being operative to cause one or more power consuming events, each power consuming event being associated with a respective weight. The integrated circuit also comprises at least one accumulation block for monitoring the functional blocks over a time window and generating a weighted count of the number of occurrences of each power consuming event within the time window; and a power calculation module for calculating a runtime power consumption estimate over the time window using the weighted count. The weighted count may comprise a sum of products of each one of the power consuming events by its respective weight. Calculating the runtime power consumption estimate may comprise averaging the weighted count over the time window to generate a dynamic power estimate, calculating a leakage power estimate over the time window, and summing the dynamic power estimate with the leakage power estimate.

Abstract: Technologies for a basic input/output system (BIOS) firmware that can take different boot paths depending on the operating system that a user selects to boot within a computer system are described herein. Each boot path can handle initialization differently based upon the needs of the operating system and overall project design. A method for supporting multiple boot paths on a computer includes receiving a boot path indicator that indicates a boot path to be executed. Once the boot path indicator is received, the boot path corresponding to the boot path indicator is executed and an operating system corresponding to the boot path indicator is booted.

Abstract: A method is provided for synchronizing time in an unsynchronized vehicle controller area network system. A master control unit receives a global time from a time synchronization source. The master control unit estimates a respective time delay in transmitting messages by electronic control units on each controller area network bus. The time delay is a difference between a time when a message is generated by a respective electronic control unit for transmission on a respective controller area network bus and a time when the message is transmitted on the respective controller area network bus. The global time is adjusted for each respective controller area network bus based on the estimated time delays associated with each respective controller area network bus. Global time messages from the master control unit are transmitted to each electronic control unit that include the adjusted global times for an associated controller area network bus.

Abstract: A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period TP to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal with a delay resolution of TP/N seconds over a range spanning TP seconds to produce pulses of an output signal. The second coarse delay circuit delays pulses of the output signal of the first coarse delay circuit over a range spanning TP seconds with a delay resolution of TP/M seconds to provide pulses of the clock signal with a timing resolution of TP/(M*N) seconds when the integers N and M are relatively prime.

Abstract: A method for reset a register includes the following step: a computer starts to be booted and perform a booting procedure. Wherein, the computer includes at least one register. Power is supplied to the at least one register. Determine if the computer is booted successfully. If it is determined that the computer fails to be booted, the at least one register is kept to be grounded for a predetermined period of time to reset the at least one register. After the at least one register is grounded, power is supplied to the at least one register again, and the computer is rebooted.

Abstract: The present invention relates to platform power management. In some implementations, platform tasks, that require servicing by a host processor, may be serviced in groups to create longer or more idle periods to enable the host processor to be in lower power consuming states more often.

Abstract: A processor includes a first virtual terminal, a second virtual terminal, circuitry coupled to the first virtual terminal for providing current to the first virtual terminal, a first regulating transistor coupled between the first virtual terminal and the second virtual terminal, a first disabling transistor coupled in parallel with the first regulating transistor for selectively disabling the first regulating transistor by directly connecting the second virtual terminal to the first virtual terminal, a second regulating transistor coupled between the second virtual terminal and a first power supply voltage terminal, and a second disabling transistor coupled in parallel with the second regulating transistor for selectively disabling the second regulating transistor by directly connecting the second virtual terminal to the first power supply voltage terminal.

Abstract: A data processing system includes a central processing unit (CPU) and a memory coupled to the CPU. The memory includes an operating system (OS) adapter component, which comprises information specific to a particular operating system; an OS-independent processor component, which, when executed by the CPU, generates initialization code for a target processor using information from the OS adapter component, wherein the initialization code is specific to the particular operating system; and an OS-independent peripheral component, which, when executed by the CPU, generates driver code using information from the OS adapter component, wherein the driver code is specific to the particular operating system and the target processor.

Abstract: A system and method of storing a default function from among possible functions to be executed by a device, and executing the default function after a pre-defined interval, if during the interval a user does not respond to a notification of the upcoming execution of the default function, through the user's providing a signal of his desire not to execute the default function.

Abstract: Example embodiments relate to storage devices, computing devices, and machine-readable storage media that optimize storage device operating parameters for desktop and notebook computing devices. Example embodiments allow for optimization of operating parameters of a storage device for one of a desktop computing device and a notebook computing devices based on provision of a command to the storage device. In example embodiments, upon receipt of such a command, the storage device may reconfigure its operating parameters to be optimized for the particular type of system.

Abstract: A method for operation system startup includes steps of switching on hardware startup; determining whether there is a trigger signal; reading an initial parameter from a storage device, and loading the initial parameter into a startup program when there is no trigger signal, executing the startup program; and entering operational system.

Abstract: Methods, systems, and non-transitory computer readable media for advanced power management for serial advanced technology attachment (SATA)-based storage devices are disclosed. According to one aspect, the subject matter described herein includes a method for advanced power management of SATA-based storage devices. The method includes, at a SATA-based storage device having a controller, a non-volatile memory for storing data, and a communication interface for communicating with a host, receiving from the host a command to enter a quiescent mode. In response to receiving the command to enter a quiescent mode, the storage device enters a quiescent mode. The storage device receives from the host an indication that the storage device should enter a low power mode. In response to this indication, the storage device puts at least a portion of the non-volatile memory into a low power mode while maintaining at least a portion of the controller in normal power mode.

Abstract: A pre-boot loader reduces the boot time of an operating system (OS). An OS is typically loaded by its own OS loader. A pre-boot loader is typically a software module in the system firmware or the pre-boot environment that loads the OS loader, which in turn loads the OS. In one embodiment, the pre-boot loader bypasses part or all of the steps performed by the OS loader, which shortens the loading time of the OS loader and the OS. In another embodiment, bypassing the steps of the OS loader reduces dependency on the system firmware functions. The system firmware takes advantage of this to further reduce boot time, by executing the pre-boot loader earlier instead of waiting until the full completion of system initialization by the system firmware.

Abstract: Embodiments described herein include a method and system for synchronizing clocks between coupled integrated circuits (ICs) in a computer system. According to an embodiment, a dedicated timing pin is provided on a first IC. The first IC configures a second IC to change a pin assignment, so that the second IC interprets a signal sent on the timing pin by the first IC and received on the reassigned pin as a request to transmit a return signal. The return signal is received on the timing pin. The return signal is used to determine whether timing should be adjusted by the first IC. In an embodiment a clock and data recover (CDR) circuit compares the signal sent to the signal received in order to make the determination. In an embodiment the first IC is a processor-based device, and the second IC is a memory device controlled by the first device.