Patents Examined by Tim Phan
  • Patent number: 7337532
    Abstract: A method of manufacturing a micro-electromechanical device is provided. The method comprises providing a substrate incorporating drive circuitry, and forming a drive member, a motion-transmitting member and a working member on the substrate as discrete components. The drive member is formed to have an electrical circuit in electrical contact with the drive circuitry for receiving an electrical signal therefrom, a fixed end fast with the substrate and a free end arranged to be displaced relative to the substrate on receipt of the electrical signal by the electrical circuit. The motion-transmitting member is formed to be fast with the free end of the drive member so that the motion-transmitting member is displaced together with the free end. The working member is formed to be fast with the motion-transmitting member so that the working member is displaced with the motion-transmitting member to perform work.
    Type: Grant
    Filed: December 10, 2004
    Date of Patent: March 4, 2008
    Assignee: Silverbrook Research Pty Ltd
    Inventor: Kia Silverbrook
  • Patent number: 7337524
    Abstract: A method of forming a winding core for an electric motor includes providing a hollow jig having a guide, sliding plates, each having a guide and a central opening, onto the guide in the jig where the guides mate, and pressing a shaft into the central opening of the plates. The plates are then compressed to form a lamination and secured in compression by a lock nut on the shaft.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: March 4, 2008
    Assignee: Neodrive LLC
    Inventor: Laurens Wolters
  • Patent number: 7334318
    Abstract: A method of manufacturing an inexpensive fine resistor which do not require dimensional classifications of discrete substrates is disclosed. The method eliminates a process of replacing a mask according to a dimensional ranking of each discrete substrate. The method includes: dividing an insulated substrate sheet along a first slit dividing portion and a second dividing portion perpendicular to the first dividing portion; forming a top electrode layer on a top face of the discrete substrate; forming a resistor layer such that a part of the resistor layer overlaps the top electrode layer; forming protective layers so as to cover the resistor layer; and forming side electrode layer on a side face of the discrete substrate such that the side electrode layer is electrically coupled to the top electrode layer.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: February 26, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masato Hashimoto, Yoshiro Morimoto, Akio Fukuoka, Hiroaki Kaito, Hiroyuki Saikawa, Toshiki Matsukawa, Junichi Hayase
  • Patent number: 7334316
    Abstract: A method of sealing a generator stator bar and a stator bar end fitting receiving the end including the steps of: brazing the fitting to the end of the stator bar with a braze material; applying a metallic barrier coating material to the end of the stator bar in the fitting; heating the fitting at a temperature at least as hot as a liquidus temperature of the metallic coating material and cooler than a solids temperature of the braze material; coating the end of the stator bar in the fitting with liquid metallic barrier coating material, and solidifying the liquefied metallic coating material to form a metallic barrier coating on the end of the stator bar in the fitting.
    Type: Grant
    Filed: July 28, 2004
    Date of Patent: February 26, 2008
    Assignee: General Electric Company
    Inventors: Yu Wang, Jeffrey Michael Breznak, Lawrence Lee Sowers
  • Patent number: 7334320
    Abstract: Tolerance to ESD is increased in an electronic fuse by providing at least one non-conductive region adjacent to a conductive region on the surface of an insulator. Such an arrangement reduces the thermal stresses imposed on the insulator in high current applications. Where multiple conductive and adjacent non-conductive regions are disposed on an insulator, the fuse can fail in discrete steps, thus providing a well defined and easily detected transisition to a blown state, as well as providing a stepwise increase in resistance between prescribed resistance values.
    Type: Grant
    Filed: December 7, 2004
    Date of Patent: February 26, 2008
    Assignee: International Business Machines Corporation
    Inventor: Steven H. Voldman
  • Patent number: 7334327
    Abstract: A method of manufacturing a RF connector includes the following steps. First, a first workpiece with first assembly units is provided. Each first assembly unit includes a first joint piece with a first joint portion, a metal shell with a ring and soldering tags extending therefrom, and a first connection portion connecting the first joint piece and the ring. Next, a second workpiece with second assembly units is provided. Each second assembly unit includes a second joint piece with a second joint portion, a center contact with a base and a center pin disposed thereon, and a second connection portion connecting the second joint piece and the base. Then, the first and second joint portions are positioned to contact with each other and then riveted together. Then, dielectric bodies are formed to at least correspondingly cover part of each ring and each base. Thereafter, a singularizing process is performed.
    Type: Grant
    Filed: August 14, 2006
    Date of Patent: February 26, 2008
    Assignee: Speed Tech Corp.
    Inventors: Li-Sen Chen, Wen-Hsing Zhang, Jia-Wei Li
  • Patent number: 7334324
    Abstract: A method of manufacturing a, in order to accommodate the words range and to clarify the multilayer wiring board, grooves for forming a wiring circuit and via holes are formed in an insulating substrate formed from a thermoplastic resin composition comprising a polyarylketone resin with a crystalline melting peak temperature of at least 260° C. and an amorphous polyetherimide resin as the primary constituents, a metallic foil is embedded within the grooves so that the surface of the foil protrudes to the surface of the insulating substrate, and a conductive material formed by curing a conductive paste is used for filling the via holes.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: February 26, 2008
    Assignees: Sony Corporation, Mitsubishi Plastics, Inc.
    Inventors: Minoru Ogawa, Masahiro Izumi, Shigeyasu Itoh, Shingetsu Yamada, Shuuji Suzuki, Hiroo Kurosaki
  • Patent number: 7334319
    Abstract: The aim of the invention is to improve the breaking ability of vacuum interrupter in the medium- and high-voltage range. Said aim is achieved whereby the contact pieces which may be displaced relative to each other are moved with a relatively high speed during a first phase (S1) of the separation process until about ¼ to ½ of the ultimate separation (extinction stroke Eh) and are brought to the given ultimate separation (isolating stroke Eh) during a second phase (S2) with relatively low speed.
    Type: Grant
    Filed: June 6, 2001
    Date of Patent: February 26, 2008
    Assignee: Siemens Aktiengesellschaft
    Inventors: Joerg Kusserow, Roman Renz
  • Patent number: 7325302
    Abstract: A method of forming an interconnection element. In one embodiment, the interconnection element includes a first structure and a second structure coupled to the first structure. The second structure coupled with the first material has a spring constant greater than the spring constant of the first structure alone. In one embodiment, the interconnection element is adapted to be coupled to an electronic component tracked as a conductive path from the electronic component. In one embodiment, the method includes forming a first (interconnection) structure coupled to a substrate to define a shape suitable as an interconnection in an integrated circuit environment and then coupling, such as by coating, a second (interconnection) structure to the first (interconnection) structure to form an interconnection element. Collectively, the first (interconnection) structure and the second (interconnection) structure have a spring constant greater than a spring constant of the first (interconnection) structure.
    Type: Grant
    Filed: May 23, 2006
    Date of Patent: February 5, 2008
    Assignee: FormFactor, Inc.
    Inventors: Gaetan L. Mathieu, Benjamin N. Eldridge
  • Patent number: 7325299
    Abstract: A method of making a circuitized substrate. A conductive layer having a substantially planar upper surface is formed on and in direct mechanical contact with an upper surface of a substrate. A portion of the conductive layer is removed to form an interim side wall in the conductive layer. A layer of patternable material is formed on the substantially planar upper surface and on the interim side wall. A portion of the layer of patternable material on the conductive layer is removed to expose the interim side wall. A portion of the substantially planar upper surface is removed to form a side wall in the layer of patternable material. Portions of the interim side wall in the conductive layer are removed to form a second side wall and a bottom wall defined by the upper surface of the substrate. The second side wall is substantially perpendicular to the bottom wall.
    Type: Grant
    Filed: January 4, 2007
    Date of Patent: February 5, 2008
    Assignee: International Business Machines Corporation
    Inventors: Frank D. Egitto, Kevin T. Knadle, Andrew M. Seman
  • Patent number: 7322099
    Abstract: A method for producing components for injection moulding comprising a body made of thermally conducting material with expansion coefficient matching that of the insulating layers and provided with a passage for the material to be injected. At least one strip of electrically conducting material with high change of resistance with temperature, forming a heating resistor or inductor is applied on a electrically insulating base layer previously directly applied on the body. At least one final insulating layer with low thermal emissivity is then applied to optimise electrical efficiency. The method utilises thermal spray techniques and can be applied also for production of other heating equipment.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: January 29, 2008
    Assignee: Inglass S.p.A.
    Inventors: Gianfranco Cirri, Maria Prudenziati
  • Patent number: 7316063
    Abstract: A method of fabricating a substrate is disclosed. Apertures are formed in a substrate blank. A conductive layer is formed on opposing surfaces of the substrate, as well as inside the apertures. Conductive elements are defined on one or both opposing surfaces by masking and etching. Additional layers of conductive materials may be used to provide a barrier layer and a noble metal cap for the conductive elements. The methods of the present invention may be used to fabricate an interposer for use in packaging semiconductor devices or a test substrate. Substrate precursor structures are also disclosed.
    Type: Grant
    Filed: January 12, 2004
    Date of Patent: January 8, 2008
    Assignee: Micron Technology, Inc.
    Inventors: Warren M. Farnworth, Steven M. McDonald, Nishant Sinha, William M. Hiatt
  • Patent number: 7305754
    Abstract: In manufacturing a chip resistor by dividing a chip resistance substrate which includes an insulator, resistance film formed on a surface of the insulator, and a plurality of conductive strips disposed on the resistance film at fixed intervals, grooves are formed by removing a predetermined width of the resistance film including at least second prescribed severing lines. After forming the grooves, the chip resistance substrate is severed in longitudinal and lateral directions along first prescribed severing lines for dividing the conductive strips into two parts and the second prescribed severing lines perpendicular to the first prescribed severing lines so as to produce discrete chip resistors.
    Type: Grant
    Filed: November 18, 2004
    Date of Patent: December 11, 2007
    Assignee: Disco Corporation
    Inventors: Kazuma Sekiya, Toshiaki Takahashi
  • Patent number: 7302752
    Abstract: A method of making and using an extended test switch starting with a previously existing un-extended test switch that is ready for connection to electrical devices to be tested. A housing selected from one or more available housings each having a predetermined length is connected to a modified un-extended test switch. Each housing has a rear wall that has several inwardly and outwardly facing terminals. At least one of the rear facing terminals of the un-extended test switch is connected to an associated one of the inwardly facing terminals of the housing. After manufacture the extended test switch can be mounted in a suitable receptacle for connection to at least one electrical device. One or more of the switches on the front of the un-extended test switch to be left in an operational condition with a clear cover attached to the front of the test switch.
    Type: Grant
    Filed: September 23, 2004
    Date of Patent: December 4, 2007
    Assignee: ABB Inc.
    Inventor: Roy Ball
  • Patent number: 7302749
    Abstract: The method of making a two-layer lap winding (12) for a multiphase electrical machine includes the steps of winding a first coil unit (20) of a first phase winding (14) around a winding bar (10); subsequently laying a coil connector (18) of the first phase winding (14) in a first direction and then winding at least one other coil unit (16) of at least one other phase winding (14) around the winding bar (10) and over the coil connector (18). Subsequently a second coil unit (22) of the first phase winding (14) is wound around the winding bar (10) following all first coil units of all phase windings and after all coil connectors from the first coil units are laid. A method of making a stator from the two-layer lap winding (12) is also described.
    Type: Grant
    Filed: May 10, 2004
    Date of Patent: December 4, 2007
    Assignee: Robert Bosch GmbH
    Inventors: Helmut Kreuzer, Eberhard Rau, Reinhard Bezner
  • Patent number: 7299538
    Abstract: The present invention relates to micro-electro-mechanical systems (MEMS). The present invention relates to a design feature that allows lower actuation voltage for electrostatically actuated structures (i.e., switches or mirrors). The present invention further relates to a method for fabricating such a design that allows lower actuation voltage.
    Type: Grant
    Filed: October 14, 2004
    Date of Patent: November 27, 2007
    Assignee: Wispry, Inc.
    Inventor: Svetlana Tactic-Lucic
  • Patent number: 7290333
    Abstract: A conductive film has a plurality of clearances (openings) and a plurality of auxiliary clearances. The plurality of clearances and the plurality of auxiliary clearances are formed to have such numerical apertures and locations that generate no bias in the distribution of conductive film in consideration of the entire conductive film. The conductive film can disperse stress caused by thermal expansion etc., to ease by having the plurality of clearances and the plurality of auxiliary clearances. Accordingly, the conductive film is less prone to being peeled off the insulating film. Further, since the distribution of conductive film is substantially uniform as a whole, the transfer characteristics that are fixed by the distribution become substantially uniform as a whole.
    Type: Grant
    Filed: December 3, 2004
    Date of Patent: November 6, 2007
    Assignee: NEC Corporation
    Inventor: Isao Matsui
  • Patent number: 7290328
    Abstract: Major surface of a substrate having an optical waveguide and a modulation electrode is pasted to a base substrate through a thermosetting resin, and then the rear surface of the substrate is machined thus making thin the entirety. Subsequently, the rear surface of the substrate thus rendered thin is subjected to machining or laser machining to form a thin part, which is further subjected to machining or laser machining to form a first thin part at a part, including the optical waveguide, of the thin part and a second thin part thinner than the first thin part contiguously thereto. Thereafter, the rear surface of the substrate is pasted to the major surface of a supporting substrate through a thermosetting resin and the base substrate is stripped thus obtaining an optical modulator.
    Type: Grant
    Filed: September 16, 2004
    Date of Patent: November 6, 2007
    Assignee: NGK Insulators, Ltd.
    Inventors: Jungo Kondo, Yukio Mizuno, Minoru Imaeda, Atsuo Kondo
  • Patent number: 7287320
    Abstract: A method for programming a routing layout design through one via layer includes forming a plurality of metal traces on a first routing layer and a second routing layer, and positioning a plurality of vias within a via layer disposed between the first and second routing layers for connecting the metal traces on the first and second routing layers according to a first current route defined by a predetermined circuit layout design to connect a first node and a second node so as to establish a second current route equivalent to the first current route.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: October 30, 2007
    Assignee: Faraday Technology Corp.
    Inventors: Hsin-Shih Wang, Shang-Jyh Shieh, Ming-Hsin Ku
  • Patent number: 7287328
    Abstract: Methods for injecting charge include providing a target comprising a first layer on a second layer, coupling a conductive base to the second layer, and providing a medium which is in contact with at least a portion of the first layer. An electrode is positioned to face and is spaced from the first layer and is at least partially in contact with the medium. An electric field is provided across the first and second layers to inject charge to an interface between the first layer and the second layer.
    Type: Grant
    Filed: August 24, 2004
    Date of Patent: October 30, 2007
    Assignee: Rochester Institute of Technology
    Inventor: Michael D. Potter