Abstract: Disclosed is an adapter. The adapter may include a first end, a second end, a housing, and a logic circuit. The first end may be operative to connect to a terminal device. The second end may be operative to connect to a peripheral device. The housing may connect the first end to the second end. The logic circuit may be located within the housing and electrically couple the first end to the send end. The logic circuit may be operative to perform a handshake operation between the terminal device and the peripheral device to determine compatibility between the terminal device and the peripheral device.

Abstract: A method for remotely triggered reset of a baseboard management controller (BMC) of a computer system is disclosed. The computer system includes a first computer node, a second computer node and a control unit. The method includes: (A) receiving, by a first BMC of the first computer node, from a computer device and via a network, a reset command which indicates that reset of a second BMC of the second computer node should be triggered; (B) transmitting, by the first BMC and to the control unit, a control signal that corresponds to the reset command; and (C) transmitting, by the control unit and to the second BMC, a reset signal that corresponds to the control signal, so as to trigger reset of the second BMC.

Abstract: Methods, systems, and computer-readable media for batch registration and configuration of devices are disclosed. A plurality of devices are detected over one or more networks. Data indicative of the plurality of devices is provided through a user interface. Through the user interface, user input is received that indicates a selected plurality of the devices. The selected plurality of the devices are registered with a service provider environment. The selected plurality of the devices are authenticated using device-specific credentials and registered for device-specific accounts with the service provider environment. A configuration profile is deployed to the selected plurality of the devices.

Abstract: Methods and apparatus for augmenting routing resources. In one exemplary embodiment, a Thunderbolt™ transceiver incorporates a Peripheral Component Interconnect Express (PCIe) bus that supports hot-plugging and hot-unplugging of peripheral devices. Unfortunately, for various backward compatibility reasons, existing PCIe bus enumeration protocols can quickly exhaust the PCIe routing resources (for example, PCIe bus numbers) resulting in undesirable consequences (for example, crashes, dead connections, etc.) The present disclosure describes schemes for augmenting the pool of PCIe bus numbers and dynamically re-assigning PCIe bus numbers, so as to eliminate the aforementioned concerns.

Abstract: A link controller, method, and data processing platform are provided with dual-protocol capability. The link controller includes a physical layer circuit for providing a data lane over a communication link, a first data link layer controller which operates according to a first protocol, and a second data link layer controller which operates according to a second protocol. A multiplexer/demultiplexer selectively connects both data link layer controllers to the physical layer circuit. A link training and status state machine (LTSSM) selectively controls the physical layer circuit to transmit and receive first training ordered sets over the data lane, and inside the training ordered sets, transmit and receive alternative protocol negotiation information over the data lane. In response to receiving the alternative protocol negotiation information, the LTSSM causes the multiplexer/demultiplexer to selectively connect the physical layer circuit to the second data link layer controller.

Abstract: An infant care station that includes multiple operational modules that communicate with each other to carry out the infant care station functions. The multiple modules form part of a micro-environmental platform that allows for communication and power connections between all of the operational components required within the infant care station. The multiple modules communicate with each other utilizing a universal interface bus that includes power connections, communication connections and control connections between the multiple modules. Sensor data obtained by various sensors is stored using a standard data format. A data repository is included in one of the modules and is used to store sensor data obtained from the infant patient, operational protocols and other information needed to operate the infant care station. The data repository provides a central location for both data producers and data subscribers that are part of the micro-environment platform.

Abstract: Various examples of the present technology provide systems and methods for incorporating a switch card and adapter cards in a server system to provide flexible HDD and SSD supports. More specifically, a server system comprises a switch card having at least two different types of interfaces (e.g., a Serial Attached SCSI (SAS) interface, a serial ATA (SATA) interface, or a Peripheral Component Interconnect Express (PCIe) interface), and a controller that comprises a first Central Processing Unit (CPU) and a second CPU. The first CPU is connected to a first adapter card while the second CPU is connected to a second adapter card. The first adapter and the second adapter are coupled to the switch card of the server system.

Abstract: A system is configured to use a de-randomizer and budget data structure to economize I/O operations for a shared storage device while still allowing access to the device to a number of different entities. Embodiments can identify a comparatively low cost next operation as compared to other I/O operations, including a cost for seek time, for a first entity to dispatch to the storage device when the first entity has sufficient budget to have the I/O operation performed on its behalf and to identify an I/O operation for a second entity to dispatch to the storage device when there is insufficient budget for the first entity.

Abstract: A method determines a configuration for inter-processor communication for a heterogeneous multi-processor system. The method determines at least one subgraph of a graph representing communication between processors of the heterogeneous multi-processor system. For each subgraph the method (i) determines a plurality of subgraph design points. Each subgraph design point has a variation of channel mapping between any two of the processors in the subgraph by selecting from first-in-first-out (FIFO) memory and shared cache, and varying the shared cache and a local memory associated with at least one of the processors according to the channel mapping; and (ii) selects a memory solution for the subgraph, based on a cost associated with the selected memory solution. The method then determines a configuration for the graph of the heterogeneous multi-processor system, based on the selected memory solutions, to determine the configuration for inter-processor communication for the heterogeneous multi-processor system.

Abstract: A storage controller coupled to a storage array includes a device driver running in a kernel space that receives an administrative command from an application running in a user space of the storage controller and writes the administrative command to a first submission queue of a plurality of submission queues associated with a storage device in the storage array, where the first submission queue is reserved for use by the device driver. An input/output (I/O) command received from the application running in the user space, however, is written directly to a second submission queue of the plurality of submission queues without being routed through the kernel space, where the second submission queue being reserved for direct access by the application running in the user space.

Abstract: A smart add-in card can be leveraged to perform testing on a host server computer. The add-in card can include an embedded processor and memory. Tests can be downloaded to the add-in card to test analog features of a communication bus between the host server computer (motherboard) and the add-in card. In a particular example, a PCIe communication bus couples the motherboard to the add-in card and the tests can test a connection or communication link negotiated between the add-in card and another device using the PCIe communication bus. The tests can be developed to test errors that are typically difficult to test without the use of special hardware. However, the smart add-in card can be a simple Network Interface Card (NIC) that resides on the host server computer during normal operation and is used for communication other than error testing.

Abstract: A device includes a connector including first and second portions, each being configured to establish an independent data connection with a portion of first and second connectors in an external device, and a controller. When the first portion is connected with a third portion of the first external connector, and a request to connect with the second portion is received from the second external connector, the controller determines whether or not to accept the request, and transmit an acceptance signal or a rejection signal to the second external connector through the second portion, according to the determination result.

Abstract: A clustered storage system in one embodiment comprises a plurality of nodes, with each of at least a subset of the nodes comprising a set of processing modules configured to communicate over one or more networks with corresponding sets of processing modules on other ones of the nodes. In conjunction with a failure of a first instance of a process running on a given one of the nodes and a subsequent restart of a second instance of the process, at least one of the processing modules is to identify at least one transfer buffer command of the first instance of the process, to identify a plurality of logically ordered commands of the first instance of the process, and to provide distinct treatment of the transfer buffer command relative to treatment of the logically ordered commands in a manner that ensures that the restart of the second instance of the process is not delayed to await completion of the transfer buffer command or the logically ordered commands.

Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices for a control unit managing access by hosts to logical devices configured with capacity from attached physical devices. An alias management group of logical devices and alias addresses assigned to the logical devices is configured. A plurality of requests to establish an association of the host with a logical device and the alias addresses assigned to the logical devices in the alias management group are received from a host. Acknowledgment is made to the host that the association is established in response to determining that the host is assigned the logical devices and alias addresses of the logical devices in the alias management group. The host can use one available alias address assigned to any one of the logical devices to access any one of the logical devices indicated in the association.

Abstract: An apparatus includes an interface and a circuit. The interface may be connectable to (i) a plurality of counters and (ii) multiple pipelines. The circuit may be configured to (i) increment two or more given counters of the counters associated with a plurality of first data units in response to the first data units being available in a buffer, where two or more of the pipelines each (a) reads a plurality of current units from the first data units and (b) decrements a respective one of the given counters in response to each read of one of the current units, (ii) monitor the decrements of the given counters and (iii) block a second data unit from being copied into the buffer until all of the given counters indicate that the buffer has room to hold the second data unit.

Abstract: A memory circuit is configured for storage of completion queues. Each completion queue can store completion descriptors associated with transfers of data from interrupt source circuits to the memory circuit. A direct memory access circuit provides access to the memory circuit for the interrupt source circuits. An interrupt engine issues interrupt messages for processing the completion descriptors in the completion queues in response to satisfaction of a set of trigger conditions specified in an active interrupt moderation mode. The active interrupt moderation mode is one of multiple available interrupt moderation modes. The interrupt engine bypasses issuing interrupt messages in response to the set of trigger conditions of the active interrupt moderation mode not being satisfied.

Abstract: Interruption facility for adjunct processor queues. In response to a queue transitioning from a no replies pending state to a reply pending state, an interruption is initiated. This interruption signals to a processor that a reply to a request is waiting on the queue. In order for the queue to take advantage of the interruption capability, it is enabled for interruptions.

Abstract: The present invention provides an all-in-one machine, a method for the all-in-one machine to realize quick touch in all channels, and a computer storage medium. The method includes: detecting which channel is currently connected to the main board, and controlling a USB selecting switch to connect a first data port of a touch frame with a USB port of a device or module to which the currently connected channel belongs, based on the detected channel information; determining whether there is an action to call a touch menu when detecting that the channel connected to the main board is an internal PC module channel or an external device channel; and if so, activating the main board to start a touch menu application program, and making response, by the main board, to touch data within an area of the touch menu transmitted from the touch frame through the second data port, after the touch menu has been called and before an action of leaving the touch menu is detected.

Abstract: The invention relates to a system and to a method for identifying a compression roller column in a tableting machine having a machine processor. The system includes a plug-in connection which includes a receiving socket and a plug. The plug has at least one embedded controller, and data can be exchanged between the machine processor of the tableting machine and the embedded controller of the plug via the one plug-in connection. The plug and the receiving socket are arranged on the tableting machine. The plug can be connected to the receiving socket.

Abstract: Mechanisms and techniques for configuring a configurable slave device using a high speed serial link where a different number of lanes of the high speed serial link are used to send data between the slave device and a master device, depending on whether the slave device is in configuration mode or in normal operations mode, are provided.