Abstract: The first information processing apparatus is configured to detect the removal device attached to the removal device interface, and send, to the second information processing apparatus, a mount request to mount the removal device, the second information processing apparatus is configured to receive the mount request from the first information processing apparatus, mount, on the second information processing apparatus, the removal device attached to the removal device interface of the first information processing apparatus, and send a mount point identifier to the first information processing apparatus, the mount point identifier being an identifier indicating a mount point of the removal device mounted on the second information processing apparatus, and the first information processing apparatus is further configured to receive the mount point identifier from the second information processing apparatus, and mount the mount point of the second information processing apparatus indicated by the mount point ident

Abstract: A recording medium to be used by being connected to a digital device includes a local bus, a plurality of recording units, an information storage unit, and a communication unit. The local bus has a plurality of switches or bridges. The plurality of recording units are connected to the local bus. The information storage unit stores information indicating a bus configuration of the local bus. The communication unit is used for transferring the information to and from the digital device. After the recording medium is inserted into the digital device, the bus configuration of the local bus is reconstructed based on the information acquired from the communication unit via the information storage unit by the digital device.

Abstract: A memory system memory system includes a first chip configured to perform a first operation, a second chip configured to perform a second operation, and a stacked memory device including a stacked structure of a plurality of memories. The stacked memory device being configured to be accessed by the first chip and the second chip through a shared bus.

Abstract: A data management method includes allocating a buffer for an application based on request information associated with data requested by the application, storing sensor data corresponding to the request information in the buffer, and transferring the sensor data stored in the buffer to the application.

Abstract: The present disclosure provides a swappable card module for a computer component. The swappable card module can be configured to positioned in either the front side or back side of a server system. Some examples of the present disclosure provide for a card module holding at least one computer card, an adapter board, and a module housing.

Abstract: Various embodiments are directed to a USB hub configured for supporting multiple data transfer speed protocols. The USB hub comprises a plurality of protocol/LINK layer components; and a physical layer component shared among the plurality of protocol/LINK layer components and supporting at least two USB connection ports. The physical layer component is in communication with each of the plurality of protocol/LINK layer components. A buffer system (including RX/TX buffers) is shared among the plurality of protocol/LINK layer components and a USB host controller component is in communication with the buffer system. The physical layer component is configured for operating in a first mode to support one of the at least two USB ports in a first operating mode; and operating in a second mode to support the at least two USB ports in a second operating mode.

Abstract: According to one embodiment, a storage device includes a nonvolatile memory, controller and interface. The nonvolatile memory stores data. The controller controls the operation of the nonvolatile memory. The interface includes first and second input/output units that transmit and receive a signal with respect to a host device. The first and second input/output units are set on the first hierarchy having the same communication function. The interface issues a connection request to the first input/output unit and when the connection request to the first input/output unit is rejected, the interface issues the connection request to the second input/output unit.

Abstract: A storage device includes a controller and a nonvolatile memory device. The controller includes a field programmable gate array (FPGA) and receives an FPGA image for updating the FPGA from an outside in response to a first command received from the outside. The nonvolatile memory device stores the FPGA image. The controller receives the FPGA image through a main interface or a sideband interface, and executes the FPGA image in response to a second command received from the outside.

Abstract: A storage controller includes a plurality of submission queues corresponding to an initiator device and a processing device, the processing device to receive a Fibre Channel Protocol (FCP) command from the initiator device and send the FCP command to a first submission queue of the plurality of submission queues, the first submission queue being reserved for use by a kernel space of the storage controller. The processing device further to receive a Non-Volatile Memory Express over Fibre Channel (NVMe/FC) command from the initiator device. The processing device further to send the NVMe/FC command to a second submission queue of the plurality of submission queues without routing the NVMe/FC command through the kernel space, the second submission queue being reserved for direct access by the initiator device to a user space of the storage controller.

Abstract: A memory system includes a non-volatile memory, a data buffer in which data read out from the nonvolatile memory are stored prior to transmission to an initiator that is requesting the data, a port through which the initiator sends a request for the data and through which the data in the data buffer are transmitted to the initiator. When the port is connected to a first initiator at a time both first data requested by the first initiator and second data requested by a second initiator are stored in the data buffer and the second data become ready for transmission prior to the first data, the second data are transmitted through the port prior to the first data.

Abstract: Arbitration circuitry is provided for allocating up to M resources to N requesters, where M?2. The arbitration circuitry comprises group allocation circuitry to control a group allocation in which the N requesters are allocated to M groups of requesters, with each requester allocated to one of the groups; and M arbiters each corresponding to a respective one of the M groups. Each arbiter selects a winning requester from the corresponding group, which is to be allocated a corresponding resource of the M resources. In response to a given requester being selected as the winning requester by the arbiter for a given group, the group allocation is changed so that in a subsequent arbitration cycle the given requester is in a different group to the given group.

Abstract: Embodiments of the present invention provide a connecting apparatus and a system. The connecting apparatus includes N interconnection units, M line processing units, and X switch processing units, where each interconnection unit is connected to at least one switch processing unit, each switch processing unit is connected to only one interconnection unit, each interconnection unit is connected to the M line processing units, each line processing unit is connected to the N interconnection units, M is a positive integer, N is a positive integer, and X is greater than or equal to N. In addition, the embodiments of the present invention further provide another connecting apparatus and system. According to the foregoing technical solutions, a connecting mode between an LPU and an SPU is relatively flexible.

Abstract: A method for enhancing an execution of AS5643 functions within AS5643 bus nodes. Also, at the same time, the method reduces overall software requirements and complexity of the AS5643 functions. The method includes attaching a AS5643 function block to the one or more interface layers of an IEEE-1394 serial bus. The AS5643 function block includes firmware or hardware. Further, the method provides the function block with a programmable code.

Abstract: An apparatus for recording data received in serial form is provided. The apparatus includes a data logging port, an external access port, a first memory, and a command memory and a state machine executing on a processor internal to the apparatus, that writes the data, received in serial form through the data logging port, to the first memory while locking out access to the first memory via the bus interface and the command memory. The bus interface and the command memory are configured to read the first memory, when not locked out, in accordance with a command placed in the command memory through the bus interface. A method performed by the apparatus is also provided.

Abstract: According to an embodiment, a computer system includes a main device, a first computer unit and a second computer unit. The main device includes a first accommodation portion and a second accommodation portion. The main device includes a selector switch, a first selector, a second selector and a control circuit. The first selector conducts either one of first signal lines extended from the first accommodation portion or the second accommodation portion. The second selector conducts either one of second signal lines extended from the first accommodation portion or the second accommodation portion. The control circuit controls the first selector and the second selector by the selector switch.

Abstract: A tablet information handling system keyboard stand stores pairing information in non-transitory memory accessed by an embedded controller upon detection of a physical connection with a tablet information handling system and communicated to an embedded controller in the tablet information handling system through the physical interface. Embedded controller cooperation coordinates configuration of a wireless personal area network interface without wireless communication or power applied to the wireless networking resources.

Abstract: An apparatus includes a processor and a machine-readable medium coupled to the processor and comprising instructions. The instructions, when loaded into the processor and executed, configure the processor to identify that a USB element has attached to a USB hub at a port, classify the USB element according to power operations of the USB element, and assign an upstream or downstream setting of the port based upon the classification of the USB element based on power operations of the USB element.

Abstract: An integrated circuit includes a combined serial data output and interrupt output terminal, a serial communication control circuit; an interrupt generation circuit, and an output circuit. The output circuit includes a serial data input, an interrupt input, and a combined serial data and interrupt output. The serial data input is coupled to a serial data output of the serial communication circuit. The interrupt input is coupled to an interrupt output of the interrupt generation circuit. The combined serial data and interrupt output is coupled to the combined serial data output and interrupt output terminal.

Abstract: A computer network-storage protocol system, including at least one initiator device having an initiator block layer and an initiator network layer interfacing with a first network driver; at least one target device having a target block layer and a target network layer interfacing with a second network driver; a plurality of network interface controllers (NICs) interfacing with the first network driver and the second network driver; a plurality of distinct channels, each channel establishing a connection between the initiator device and the target device and being configured to transmit packets between the initiator device and the target device, wherein each channel is mapped to only one NIC; and wherein the initiator block layer includes at least one request message buffer and at least one data message buffer.

Abstract: A processor scheduling structure, a method and an integrated circuit are provided. In accordance with at least one embodiment, the processor scheduling structure comprises a processor circuit and an operating system task aware caching (OTC) controller circuit coupled to the processor circuit. The OTC controller circuit comprises a load request timer, a load sequence queue (LSQ), and a request arbiter. The timer and the LSQ are coupled to and provide inputs to the request arbiter. The processor circuit comprises an internal memory and a processor core. The OTC controller circuit is configured to schedule processor tasks for the processor circuit in accordance with both priority-based scheduling, using the LSQ, and time-triggered scheduling, using the load request timer.