Abstract: A processing subsystem/endpoint subsystem connection configuration system includes a plurality of processing subsystems and a multi-endpoint adapter device that provides a plurality of endpoint subsystems. A bus exchange switch device couples the plurality of processing subsystems to the plurality of endpoint subsystems, and a connection configuration engine is coupled to the multi-endpoint adapter device and the bus exchange switch device. The connection configuration engine receives a connection resource request that requests connection resources for a first processing subsystem that is included in the plurality of processing subsystems. Based on the connection resource request, the connection configuration engine causes at least one of the plurality of endpoint subsystems to perform a first connection resource change operation. The connection configuration engine then configures the bus exchange switch device to provide the connection resources for the first processing subsystem.

Abstract: An Open Compute Project (OCP) module forces an electrical shutdown sequence. The OCP module integrates an eject pull mechanism that has two (2) positions. A retracted position of the two (2) positions is inaccessible from an exterior of an information handling system. A deployed position of the two (2) positions is only accessible from an interior of the information handling system. The eject pull mechanism forces the electrical shutdown sequence prior to moving or transitioning from the retracted position to the deployed position.

Abstract: The present invention is directed to a system and method that utilizes a central repository for storing and sharing Thing Description (TD) Documents with USB extensions that correspond to specific USB I/O schema. A Network Interface Module uses the USB I/O vendor and product identifications to query the central repository and download the appropriate Thing Description (TD) document for the specific USB I/O device. The Network Interface Module parses the TD document and builds the appropriate Web of Things (WoT) data architecture that establishes the interface between the network and the USB I/O device thereby allowing the USB I/O device to become an IoT device.

Abstract: In general, in one aspect, the invention relates to a method for managing pool device resources, the method including obtaining, by a distribution manager, a resource use request from a user application, wherein the user application and the distribution manager are operating on a pool device, identifying a peripheral component interconnect (PCI) bus device, wherein the PCI bus device is located on a second pool device and connected to a pool device resource on the second pool device, and initiating access to the PCI bus device using a virtual switch operating on the pool device.

Abstract: An upstream facing port device (UFP device) and a downstream facing port device (DFP device) allow a host device and a USB device to conduct SuperSpeed communication via a non-USB compliant extension medium. In some embodiments, the UFP device helps overcome increased latency by generating synthetic packets to be transmitted to the DFP device in order to pre-fetch more data packets from the USB device than requested by the host device. In some embodiments, the DFP device adjusts service interval timing or caches data packets from the host device in order to compensate for the increased latency. In some embodiments, the DFP device transmits a synthetic acknowledgement packet to the UFP device to indicate a larger amount of free buffer space than is present on the USB device to help overcome the increased latency.

Abstract: There is provided an information processing system to increase a speed of returning identification information in response to a received command in the case where an identification information requesting command is received, the information processing system including: a plurality of processing devices each of which includes a storage unit configured to store an identification information piece; a management device configured to acquire the identification information piece from each of the plurality of the processing devices; and a communication device configured to communicate with an external device. The management device writes the identification information piece acquired from each of the plurality of the processing devices into the communication device.

Abstract: A method and apparatus for generating a message interrupt. In one embodiment, the method includes writing a predefined data pattern to a predetermined source location in a memory system. One or more first data blocks are also stored in the memory system at one or more first locations, respectively. After storing the one or more first data blocks at the one or more first source locations, creating a first data structure that comprises one or more first source addresses mapped to one or more first destination addresses, respectively, and a predetermined source address mapped to a predetermined destination address, wherein the one or more first source addresses correspond to the one or more first source locations, respectively, and wherein the predetermined source address corresponds to a predetermined source location. The first data structure can be used by a DMA controller to transfer data stored at the one or more first storage locations and to transfer the predetermined data.

Abstract: An electronic device includes a memory, plural master circuits, a transmission path, a detection unit, and a reset control unit. The plural master circuits read and write data from and into the memory. Plural instructions and data are transmitted through the transmission path while buffering and arbitrating the instructions and the data. The detection unit detects a buffer overrun in the transmission path. The reset control unit performs reset control for a portion of the transmission path affected by the buffer overrun and master circuits, of the plural master circuits, affected by the buffer overrun.

Abstract: Provided are a computer program product, system, and method for sharing alias addresses among logical devices by a host accessing logical devices provisioned with a capacity from physical devices managed by a control unit. The host establishes with the control unit an association of logical devices and alias addresses assigned to the logical devices, wherein the alias addresses are associated with an alias management group. Alias address pool information is generated indicating each of the logical devices and their assigned alias addresses indicated in the association. The host uses from the alias address pool information any one of the alias addresses in the alias address pool information to access any of the logical devices associated with the same alias management group as the alias address.

Abstract: A system for detecting HDDs and in-position states of each of them includes an HDD controller, an analysis module, and a BMC chip. The HDD controller is electrically connected to the HDDs for obtaining SGPIO information and outputting testing signals comprising the SGPIO information. The analysis module receives the testing signals and generates in-position state information according to voltage levels of the testing signals. The BMC chip is electrically connected to the analysis module. The BMC chip receives the in-position state information from the analysis module and generates a detection log accordingly.

Abstract: Low noise serial interfaces with gated clock are provided herein. In certain configurations herein, a slave device of a serial interface includes a shift register for serially shifting in an interface data signal based on timing of an interface clock signal, a control circuit (for instance, a finite-state machine) for controlling the slave device, and a register bank for storing data programmed to the slave device via the serial interface. The control circuit cuts off or gates the interface clock signal in response to determining that an interface command received over the serial interface is not intended for the slave device.

Abstract: Disclosed herein is a method and Serially Attached SCSI (SAS) controller for transmitting data using SCSI. In an embodiment, a plurality of I/O operations received from a storage unit are fragmented into a plurality of blocks. Further, each of the plurality of blocks are mapped with corresponding memory drives. Thereafter, a reduced number of virtual lanes required for transmitting the plurality of blocks to the corresponding memory drives is estimated. Finally, the reduced number of virtual lanes are created for transmitting the plurality of blocks to the corresponding memory drives. In an embodiment, the present disclosure uses virtual lanes for transmitting data, thereby eliminating requirement of dedicated, physical lanes for transmitting the data. Consequently, according to embodiments of present disclosure, the SAS controller may be configured to simultaneously activate multiple virtual lanes for completing the data transmission, thereby resulting in faster and reliable data transmission.

Abstract: The application discloses an electronic device with a USB Type-C connector, which is able to be coupled to another electronic device. The electronic device includes a control unit, a switch unit and a charge conversion unit. The control unit outputs a first control signal according to a result of power supply handshaking between the electronic device and the other electronic device. The state of the first control signal determines whether the other electronic device supplies power to the electronic device. The switch unit is coupled to the control unit, and receives a supply voltage output by the other electronic device, and the switch unit determines whether to output the supply voltage according to the state of the first control signal. The charge conversion unit is coupled to the switch unit. The charge conversion unit converts the supply voltage into a target voltage to supply power to the electronic device.

Abstract: The present disclosure provides new methods and systems for input/output command rebalancing in virtualized computer systems. For example, an I/O command may be received by a rebalancer from a virtual queue in a container. The container may be in a first virtual machine. A second I/O command may be received from a second virtual queue in a second container which may be located in a second virtual machine. The rebalancer may detect a priority of the first I/O command and a priority of the second I/O command. The rebalancer may then assign an updated priority each I/O command based on a quantity of virtual queues in the virtual machine of origin and a quantity of I/O commands in the virtual queue of origin. The rebalancer may dispatch the I/O commands to a physical queue.

Abstract: A line replacement unit includes a terminal controller, and a plastic optical fiber serial interface module (POFSIM) coupled between the terminal controller and the data bus. The POFSIM is configured to transmit digital optical signals to the data bus based on electrical signals received from the terminal controller, and transmit electrical signals to the terminal controller based on digital optical signals received from the data bus.

Abstract: Various embodiments of the present technology may provide methods and apparatus for an interface. The interface may be configured to detect a hot unplug condition based on a first output voltage at an output terminal of a first buffer circuit and a second output voltage at an output terminal of a second buffer circuit, wherein the first and second buffer circuits receive a common input. The interface may further detect the hot unplug condition based on a difference of a peak magnitude of the first output voltage and a peak magnitude of the second output voltage.

Abstract: A data processing pipeline controller receives a request, from a data iterator associated with a machine learning model, for a data output of a module in the data processing pipeline, wherein each module in the data processing pipeline has an associated cache. The controller determines whether a data output of the module is stored in the associated cache and responsive to the data output being stored in the associated cache, provides the data output from the associated cache to the data iterator without processing data through the module.

Abstract: One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers of

Abstract: An integrated circuit for monitoring components of the integrated circuit, comprising: a resource monitoring circuit configured to: track activity factors for a plurality of components of the integrated circuit; evaluate the activity factors for each of the plurality of components; determine whether an activity factor for a particular component of the plurality of components exceeds a threshold; and transmit, from the resource monitoring circuit, a signal to a software element, causing the software element to deactivate the particular component and activate an alternate component, when the activity factor for the particular component exceeds the threshold and the alternate component is available to substitute for the particular component.

Abstract: An on-chip interconnect comprises control circuitry which responds to a burst read request received at an initiating requester interface, to control issuing of at least one read request to at least one target completer device via at least one target completer interface. For a chunking enabled burst read transaction, the control circuitry supports returning the requested data items to the initiating requester device in a number of data transfers, with an order of the data items in the data transfers permitted to differ from a default order and each data transfer specifying chunk identifying information identifying which portion of the data items is represented by returned data for that data transfer. For a data transfer returned to the initiating requester device based on data returned from one of a second subset of completer interfaces, the control circuitry generates the chunk identifying information to be specified by the given data transfer.