Abstract: One embodiment includes a computing device including peripheral component bus interfaces for connection to a peripheral component bus, a first integrated circuit (IC) chip comprising a processor to initiate a register setup process of the device, a second IC chip including a tile processor including multiple tiles, each tile including at least a processing core configured to generate requests to at least one of the peripheral component bus interfaces, steering configuration registers to store steering configuration data, and steering logic to steer the generated requests responsively to the steering configuration data in the steering configuration registers, and steering register setup circuitry including a multicaster and a register setup memory, wherein the processor is configured to write the steering configuration data to the register setup memory, and the multicaster is configured to multicast the steering configuration data written to the register setup memory to the steering configuration registers of

Abstract: In one or more embodiments, one or more systems, methods, and/or processes may determine a Peripheral Component Interconnect Express (PCIe) endpoint, associated with a PCIe destination endpoint identification, includes a field programmable gate array (FPGA); may access a partial configuration for the FPGA; may construct multiple packets that include the PCIe destination endpoint identification and respective portions of the partial configuration for the FPGA; and may provide the multiple packets to the PCIe endpoint. In one or more embodiments, the one or more systems, methods, and/or processes may further map at least a portion of the FPGA to a virtual machine. In one or more embodiments, the one or more systems, methods, and/or processes may further combine the portions of the partial configuration for the FPGA to reconstruct the partial configuration for the FPGA; and may further program the FPGA with the partial configuration for the FPGA.

Abstract: A system and method for generating a control bifurcation signal in accordance with the Open Compute Project (OCP) Specification. An OCP device is provided that has a bifurcation function with an input to activate a bus bifurcation function. An input/output control circuit having an output coupled to a bifurcation control line coupled to the OCP device is provided. The input/output control circuit is operable to provide a bifurcation control signal to the OCP device over the bifurcation control line during an auxiliary power phase transition period of powering-on the OCP device.

Abstract: The present disclosure relates to a communication apparatus, a communication method, a program, and a communication system that enable more reliable communication. A bus IF is constituted by a master having an initiative of communication and a slave that communicates with the master under the control of the master. Additionally, the slave is provided with a detection unit that, when detecting a change in level of a signal line representing a declaration of initiation or end of communication by the master, outputs a detection signal indicating that the change in level of the signal line representing a declaration of initiation or end of communication has been detected, and a false detection avoidance unit that invalidates output of the detection signal during a specific time slot set in advance. The present technology can be applied to, for example, a bus IF that performs communication in conformity with the I3C standard.

Abstract: Examples described herein generally relate to a layered boundary interconnect in an integrated circuit (IC) and methods for operating such IC. In an example, an IC includes a programmable logic region, a plurality of input/output circuits, a plurality of hard block circuits, and a programmable native transmission network. The programmable native transmission network is connected to and between the plurality of input/output circuits and the plurality of hard block circuits. The plurality of hard block circuits is connected to and between the programmable native transmission network and the programmable logic region.

Abstract: Extended message signaled interrupts (MSI) data are disclosed. In one aspect, MSI bits are modified to include a system level identifier. In an exemplary aspect, an upper sixteen bits of the MSI message data are modified to be the system level identifier. By providing the system level identifier within the MSI message data, an interrupt controller can verify the interrupt source.

Abstract: A data transmission medium includes first and second conductors and a first reversible plug connector coupled to a first end thereof. The first reversible plug connector includes a plurality of signal pins, a crossbar switch, a receiver, and a transmitter. In response to a first configuration state, the plurality of signal pins includes a first predetermined number of reception pins and a second predetermined number of transmission pins. The first and second predetermined numbers are different from each other and each is greater than zero. The crossbar switch couples the first predetermined number of reception pins to a first port and the second predetermined number of transmission pins to a second port. The receiver has an input coupled to the first conductor, and an output coupled to the first port. The transmitter has an input coupled to the second port and an output coupled to the second conductor.

Abstract: The present invention provides a graphics processing system, the graphics processing system comprises a central processing unit, a plurality of graphics processing units, a bus communication protocol switch and a management board. The graphics processor units are communicatively coupled to the central processing unit. The bus communication protocol switch is coupled to the graphics processing units to implement mutual communications between the graphics processor units. The management board is coupled to the bus communication protocol switch for managing the bus communication protocol switch. The bus bar communication protocol switch can maximize and equalize the peer-to-peer network communication bandwidth between the graphics processing units, and the theoretical maximum bidirectional bandwidth can reach 300 GB/s, and is capable of expanding additional eight-graphics processing units to form a sixteen-GPUs system that enables peer-to-peer network communication of any two graphics processing units.

Abstract: In a method for increasing the data rate of a bus system in which at least at times an exclusive, collision-free access of a subscriber station to a bus line of the bus system is ensured, a subscriber station for the bus system includes a communication control device for evaluating a message that was received by at least one further subscriber station of the bus system via the bus system, the communication control device including at least two RX protocol machines that are set up to use different bit timing parameter data sets in order to evaluate whether the received message is valid, the at least two RX protocol machines each being assigned a register to which the associated RX protocol machine is designed to write the result of its evaluation of the received message.

Abstract: A method for lighting a backplane lamp of multiple NVMe hard disks is provided. The method includes: transmitting a VPP address to the backplane in a cyclic manner by the controller, and analyzing the address transmitted by the controller by a programmable logic device of the backplane after a data stream transmitted by the controller is received; transmitting, by the controller, hard disk lamp lighting information of a corresponding disk position to the programmable logic device of the backplane, if a VPP address analyzed by the backplane is the same as the VPP address transmitted by the controller; and performing logical conversion on the hard disk lamp lighting information, to convert a serial data stream on the VPP signal wires into a parallel signal, lighting a backplane lamp at a corresponding port, and uploading information of a position of the hard disk to the controller.

Abstract: The present disclosure relates to a system and related methods, apparatuses, and computer program products for controlling operation of a device based on a read request. For example, a method for performing an operation in response to a read request may include a first computing device receiving a request to read a value sent to the first computing device by a second computing device via a wireless communication link between the first and second computing devices. The method may further include the first computing device determining an operation corresponding to the value. The method may additionally include the first computing device performing the operation corresponding to the value in response to the request.

Abstract: Techniques and mechanisms for performing in-memory computations with circuitry having a pipeline architecture. In an embodiment, various stages of a pipeline each include a respective input interface and a respective output interface, distinct from said input interface, to couple to different respective circuitry. These stages each further include a respective array of memory cells and circuitry to perform operations based on data stored by said array. A result of one such in-memory computation may be communicated from one pipeline stage to a respective next pipeline stage for use in further in-memory computations. Control circuitry, interconnect circuitry, configuration circuitry or other logic of the pipeline precludes operation of the pipeline as a monolithic, general-purpose memory device. In other embodiments, stages of the pipeline each provide a different respective layer of a neural network.

Abstract: Subject matter disclosed herein may generally relate to docking systems, and more particularly, to docking systems for portable computing devices such as, for example, tablet computing devices. The docking system may include (1) an enclosure for the portable computing device and (2) a base, where the enclosure can be docked to the base. A communication channel can be established between the portable computing device and the base via the enclosure and an electrical connection that exists when the enclosure is docked with the base. Through the communication channel, data such as credential data can be passed from the portable computing device to the base. The base can control whether the enclosure is permitted to be undocked from the base based on this credential data.

Abstract: The present invention relates generally to a universal programmable voltage module that activates and deactivates an electrical component based on a programmed voltage or voltage change on a multiplexed input. The universal programmable voltage module may have input circuitry for conditioning the multiplex input for a processor configured to execute instructions from a computer-readable medium; at least one control switch; power conditioning circuitry receiving power from a battery; at least one visual indicator; and switched output circuitry. Methods of operating the universal voltage module in both a momentary and a latched mode are also provided.

Abstract: The current document is directed to a family of integrated hardware controllers that provides for cost-effective, high-bandwidth, and scalable incorporation of SSDs into large, distributed-computer systems. Certain implementations of the integrated hardware controller include dual media-access controllers for connection to one or more local area networks, remote-direct-memory-access (“RDMA”) controllers for supporting RDMA protocols over the local area network, an NVMe controller that provides access to an SSD. In certain integrated-hardware-controller implementations, the RDMA and NVMe controllers are implemented in one of a field programmable gate array (“FPGA”) and application-specific integrated circuit (“ASIC”).

Abstract: A system that allows access to a virtualized device is disclosed. The system may include a device, a processor, and a communication unit coupled to the device via a communication link. The device may include hardware resources configured to be shared by multiple threads executing on the processor. The communication unit may be configured to detect a request to access the device by the processor. In response to the detection of the request, the communication unit may send one or more instructions to the device via the communication link using a communication protocol.

Abstract: A hub device enables the deployment of I2C devices in a system that also includes I3C devices. The hub has an I3C-compliant interface with which it communicates with an I3C master(s) on an I3C bus, an I2C-compliant interface with which it communicates with I2C devices on an I2C bus, and logic and memory that supports the conversion between the two domains.

Abstract: The access control circuit writes to the first storage unit a context information transmitted in one cycle from the CPU through the first bus, a context number identifying the context information, and a link context number identifying the context information transmitted from the CPU prior to the interrupt when the request for evacuating the task context information is received by the interrupt. After writing to the first storage unit, the access control circuit transfers the data including the context information and the link context number stored in the first storage unit to the second storage unit in a plurality of cycles through the internal bus (second bus) in association with the context number stored in the first storage unit.

Abstract: An apparatus and method for controlling a virtualized endpoint device are disclosed. A processor may be configured to execute instructions included in multiple execution threads. A first device may be configured to perform multiple command and data functions, and a communication unit may include a first port coupled to the first device via a first link and be configured to send instructions from the processor to the first device via the first link using a first communication protocol. The processor may be further configured to execute first and second sets of commands included in respective execution threads. The first set of commands may be associated with the plurality of command functions and the second set of commands may be associated with the plurality of data functions.

Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.